1. Introduction

Tunnel field-effect transistors (TFETs) have captivated broad attention in recent years as the leakage current, power dissipation, and subthreshold swing (SS) of TFETs are significantly reduced^{[1, 2]}. Moreover, reduced short channel effects (SCEs), weak temperature dependency and enhanced scalability are also the advantages of TFETs as compared to metal–oxide–semiconductor FETs (MOSFETs)^[3]. However, TFETs are affected by two major drawbacks: lower on-current (I_on)^[4] and ambipolar effects^[5]. In order to ameliorate ambipolar effects, some measures are recommended in the studies with using the gate–drain underlap^[6] and a light drain doping concentration^[7]. Gate–drain underlap can widen the depletion width at the channel/drain junction since it reduces the concentration of holes at the same junction. Thus, ambipolar behavior is suppressed. A lightly doped drain can increase the tunneling distance from the channel valence band to the drain conduction band, so it is also an effective method in suppressing the ambipolar effect. Recently, some novel structures of TFETs such as the dual material control gate charge-plasma-based tunnel FET (DMCG-CPTFET)^[8], and drain work function engineered doping-less charge plasma TFET^[9] are presented for the suppression of ambipolarity. To combat the issue of low current driving capability, a number of different technologies have been reported in the literature with gate work function engineering^[10], high-k gate dielectrics engineering^[11], lower bandgap materials employed in source engineering such as germanium (Ge) source^[12] and indium arsenide (InAs) source TFETs^{[13, 14]}, and some novel structures of TFETs such as gate-all-around triple metal (GAA TM) TFETs^[15], p–n–p–n TFETs^[16], a hetero-junction at the source-channel TFETs^{[17, 18]}, a hetero-stacked TFET^[19], electrically doped TFET (ED-TFET) based on polarity control^[20], and so on. Recently, ferroelectric (FE) insulator engineering of TFET has been used due to the fact that the ferroelectric gate dielectric produces a negative capacitance (NC) effect, which leads to the enhanced electric field at the source-channel junction^[21–24]. Therefore, tunneling barrier width for electron injection is reduced. Liu et al. reported the performances of an NC DG TFET with ferroelectric layer based on simulation^[25].

As is well known, device engineers are interested in the physical models as they describe the relationship between the electrical characteristics and physical parameters of the device. Therefore, it is essential to establish an analytical model for NC DG TFETs for the purpose of further improving device properties as well as optimizing the structure. Saeidi et al. modeled and simulated a ferroelectric non-volatile memory (NVM) TFETs^[26]. The model is obtained by combining the pseudo two-dimensional (2D) Poisson’s equation and Maxwell’s equation. Chowdhury et al. presented an analytical drain current model for a vertical double-gate NC TFET, but 2D effects of the device were not taken into account in the model^[27]. However, 2D effects cannot be ignored in nanoscale devices. Chowdhury et al. reported an analytical model for the NC silicon-on-insulator (SOI) TFET, but the model only reported the characteristics when the device was operated from the off-state to the on-state^[28]. Jiang et al. investigated NC Gate-all-Around TFETs by combining simulation results and the analytical model^[29], but as the device is only operated in the subthreshold region, the model does not include the effects of the channel mobile charges. However, the channel is assumed to be fully depleted, which is not valid when the devices are operated in the linear region^[18]. Therefore, it is necessary to consider the effects of the channel mobile charges in the model.

An analytical model for NC DG TFETs with ferroelectric layer is developed for overcoming the defects of the above-mentioned models. The channel potential profile is obtained by solving the non-linear Poisson’s equation with the Landau–Khalatnikov (LK) equation^[29]. The lateral and vertical electric fields can be derived from the surface potential profile. The drain current can be obtained using Kane’s model.

2. Device structure and numerical simulation method

The cross-sectional schematics of the proposed NC DG TFETs is shown in Fig. 1. L is the length of the channel, and the value is 50 nm. t_s is the thickness of the silicon film, and the value is 10 nm. t_in is the thickness of the insulator layer, and the value is 1 nm. t_f is the thickness of the ferroelectric layer. The channel is intrinsic (doping concentration, N_CH = 10¹⁶ cm⁻³), the p+ source region is doped as 10²⁰ cm⁻³ (N_S), and the doping concentration of the n+ drain region is 5 × 10¹⁸ cm⁻³ (N_D). The x-axis is along the direction of the channel, the y-axis is perpendicular to the channel direction, and the origin of the coordinate axis lies at the middle point of the boundary between the source and channel regions.

However, the simulated results for NC DG TFETs with a metal–FE–insulator–semiconductor (MFIS) structure cannot be obtained directly due to lack of a corresponding accurate FE polarization model. Jiang et al.^[29] reported that a metal–FE–metal–insulator–semiconductor (MFMIS) structure is used to take the place of the MFIS structure. NC DG TFETs with MFMIS structure and its equivalent circuit are similar to those of Fig. 1(b) in Ref. [29]. Device properties of NC DG TFETs can be calculated by combining the TCAD device simulator Silvaco Atlas^[30] with a one-dimensional (1D) LK equation. The flow diagram of the simulation is shown in Fig. 2, where the previous four steps can be implemented by Silvaco Atlas.

3. Analytical model

3.1 Calculation of potential distribution

The voltage drop across the source and drain regions can be ignored as doping concentrations are very high in these regions.

The channel potential $\varphi \left( {x,y} \right)$ is solved by the 2D Poisson equation.

$$\frac{{{\partial ^2}\varphi \left( {x,y} \right)}}{{\partial {x^2}}} + \frac{{{\partial ^2}\varphi \left( {x,y} \right)}}{{\partial {y^2}}} = \frac{q}{{{\varepsilon _{{\rm{si}}}}}}{n_{{\rm{i}}}}{\rm{exp}}\left[ {\frac{{\varphi \left( {x,y} \right) - V}}{{{V_{\rm{t}}}}}} \right],$$

(1)

where q is the electronic charge, ε_si is the permittivity of the silicon, n_i is the intrinsic carrier density, V is the electron quasi-Fermi potential, and ${V_{\rm{t}}} = kT/q$ is the thermal voltage.

$\varphi \left( {x,y} \right)$ is decomposed into a 1D component along the channel depth direction (y) and a 2D component, and it is expressed as

$$\varphi \left( {x,y} \right) = {\varphi _0}\left( y \right) + {\varphi _1}\left( {x,y} \right).$$

(2)

Using the LK equation, the charge–voltage characteristic of the ferroelectric material is expressed as

$${V_{\rm{f}}} = {a_0}Q + {b_0}{Q^3} + {c_0}{Q^5},$$

(3)

where Q is the charge per unit area of the FE layer, and V_f is the voltage across the FE layer. The coefficients a₀, b₀, and c₀ are related to the Landau parameters u, v, and w of the ferroelectric material, and also related to the thickness of the ferroelectric layer. a₀ = 2t_fu, b₀ = 4t_fv, c₀ = 6t_fw, u, v, and w are defined as Table 1 in Ref. [29]. The higher-order terms in Eq. (3) are ignored in our analytical model, because Jiang et al. reported that they are not of significance.

The equation about ${\varphi _0}\left( y \right)$ is expressed as

$$\frac{{{\partial ^2}{\varphi _0}\left( y \right)}}{{\partial {y^2}}} = \frac{q}{{{\varepsilon _{{\rm{si}}}}}}{n_{{\rm{i}}}}{\rm{exp}}\left[ {\frac{{{\varphi _0}\left( y \right) - V}}{{{V_{\rm{t}}}}}} \right].$$

(4)

${\varphi _0}\left( y \right)$ is solved using the following boundary conditions

$${\left. {\frac{{\partial {\varphi _0}\left( y \right)}}{{\partial y}}} \right|_{y = 0}} = 0,$$

(5)

$${V_{{\rm{gs}}}} - {V_{{\rm{FB}}}} - {\varphi _0}\left( {{t_0}} \right) = \frac{{{\varepsilon _{{\rm{si}}}}}}{{{\rm{}}{C_{{\rm{ox}}}}}}{\left. {\frac{{\partial {\varphi _0}\left( y \right)}}{{\partial y}}} \right|_{y = {t_0}}} + {a_0}{\varepsilon _{\rm si}}{\left. {\frac{{\partial {\varphi _0}\left( y \right)}}{{\partial y}}} \right|_{y = {t_0}}},$$

(6)

where ${t_0} = {t_{{\rm{si}}}}/2$ . When we ignore the higher-order terms in Eq. (3), the boundary condition in Eq. (6) is derived from Kirchnoff’s voltage law (KVL) along the gate-to-channel direction. In other words, the total applied gate voltage V_gs can be written as the sum of drop across ferroelectric layer ${a_0}{\varepsilon _{{\rm{si}}}}{\left. {\frac{{\partial {\varphi _0}\left( y \right)}}{{\partial y}}} \right|_{y = {t_0}}}$ , drop across interface layer $\frac{{{\varepsilon _{{\rm{si}}}}}}{{{\rm{}}{C_{{\rm{ox}}}}}}{\left. {\frac{{\partial {\varphi _0}\left( y \right)}}{{\partial y}}} \right|_{y = {t_0}}}$ , flat band voltage V_FB and surface potential ${\varphi _0}\left( {{t_0}} \right)$ . ${V_{{\rm{FB}}}} = \left( {{W_{\rm{m}}} - \chi - {E_{\rm{g}}}/2} \right)/q + {V_{\rm{t}}}{\rm{ln}}\left( {{N_{{\rm{CH}}}}/{n_{\rm{i}}}} \right)$ , where W_m is the work function of the gate metal, and χ and E_g are the electron affinity and band gap of the Si channel, respectively^[28]. Combining Eq. (4) with Eq. (5), so ${\varphi _0}\left( y \right)$ is written as

$${\varphi _0}\left( y \right) = V + {V_{\rm{t}}}{\rm{ln}}\left[ {\frac{{{B^2}}}{{2{\rm{\delta }}}}{\rm{se}}{{\rm{c}}^2}\left( {B{y}/{{t}_0}} \right)} \right],$$

(7)

where $\delta = q{n_{\rm{i}}}t_0^2/\left( {4{\varepsilon _{{\rm{si}}}}{V_{\rm{t}}}} \right)$ , V stays constant (the value is equal to V_DS) in the channel length direction (x) except near the source junction.

Combining Eq. (7) with Eq. (6), the equation about B can be expressed as

$$\begin{split}& \left( {\frac{1}{{{\rm{}}{C_{{\rm{ox}}}}}} + {a_0}} \right)\frac{{2{\varepsilon _{{\rm{si}}}}{V_{\rm{t}}}}}{{{t_0}}}B{\rm{tan}}\left( B \right) + {V_{\rm{t}}}{\rm{ln}}\left[ {\frac{{{B^2}}}{{2\delta }}{\rm{se}}{{\rm{c}}^2}\left( B \right)} \right]\\& \qquad\qquad\qquad\qquad\qquad\qquad= {{V_{{\rm{gs}}}} - {V_{{\rm{FB}}}} - V} ,\end{split}$$

(8)

where V_FB is the flat-band voltage, and C_ox is the insulator layer capacitance.

Using the separation of variables method, the 2D potential component ${\varphi _1}\left( {x,y} \right)$ of the Laplace equation can be established as

$${\varphi _1}\left( {x,y} \right) = \left( {a{\rm{exp}}\left( {\lambda x/{t_0}} \right) + b{\rm{exp}}\left( { - \lambda x/{t_0}} \right)} \right){\rm{cos}}\left( {\lambda y/{t_0}} \right),$$

(9)

where λ is the eigen value, and a and b are coefficients.

${\varphi _1}\left( {x,y} \right)$ in Eq. (9) is solved using the following boundary conditions, as shown in Eqs. (10)–(12).

$${\left. {{\varphi _1}\left( {x,y} \right)} \right|_{x = 0}} = {{V}_{\rm{s}}} - {\varphi _0}\left( y \right),$$

(10)

$${\left. {{\varphi _1}\left( {x,y} \right)} \right|_{x = L}} = {{V}_{\rm{D}}} - {\varphi _0}\left( y \right),$$

(11)

$$- {\varphi _1}\left( {x,{t_0}} \right) = \frac{{{\varepsilon _{{\rm{si}}}}}}{{{C_{{\rm{ox}}}}}}{\left. {\frac{{\partial {\varphi _1}\left( {x,y} \right)}}{{\partial y}}} \right|_{y = {t_0}}} + {a_0}{\varepsilon _{{\rm{si}}}}{\left. {\frac{{\partial {\varphi _1}\left( {x,y} \right)}}{{\partial y}}} \right|_{y = {t_0}}}.$$

(12)

The source and drain potentials are ${V_{\rm{S}}} = - {V_{\rm{t}}}{\rm{ln}}\left( {{N_{\rm{s}}}/{n_{\rm{i}}}} \right)$ and ${{V}_{\rm{D}}} = {V_{{\rm{ds}}}} + {V_{\rm{t}}}{\rm{ln}}\left( {{N_{\rm D}}/{n_{\rm i}}} \right)$ , respectively.

Combining Eq. (9) with Eq. (12), λ is expressed as

$${\rm{\lambda tan}}\left( \lambda \right) = \frac{{{C_{\rm{ox}}}{t_0}}}{{{\varepsilon _{\rm{si}}}\left( {1 + {a_0}{C_{{\rm{ox}}}}} \right)}}.$$

(13)

Using Fourier series solution, the parameters a and b obtained by Eq. (9) with Eqs. (10) and (11) are expressed as

$$a = \frac{{\left[ {{V_{\rm D}} - {V_{\rm S}}{\rm{exp}}\left( { - \lambda L/{t_0}} \right)} \right]\sin \left( \lambda \right) - {V_1}\left[ {1 - {\rm exp}\left( { - \lambda L/{t_0}} \right)} \right]}}{{\left[ {\lambda + 0.5\sin \left( {2\lambda } \right)} \right]\sinh \left( {\lambda L/{t_0}} \right)}},$$

(14)

$$b = \frac{{ - \left[ {{V_{\rm D}} - {V_{\rm S}}{\rm{exp}}\left( {\lambda L/{t_0}} \right)} \right]\sin \left( \lambda \right) + {V_1}\left[ {1 - {\rm exp}\left( {\lambda L/{t_0}} \right)} \right]}}{{\left[ {\lambda + 0.5\sin \left( {2\lambda } \right)} \right]\sinh \left( {\lambda L/{t_0}} \right)}},$$

(15)

where the value of V₁ is ${{V}_1} = \lambda \cos \left( {\lambda /2} \right){\left. {{\varphi _0}\left( y \right)} \right|_{y \,=\, 0.5{t_0}}}$ .

The lateral and vertical electric fields for the NC DG TFETs are expressed as

$$\!\!\!\begin{split} {E_x} &= - \partial {\varphi _1}\left( {x,y} \right)/\partial x \hfill \\ & = - \left[ {{a}\lambda /{{t}_0}{\text{exp}}\left( {\lambda {x}/{{t}_0}} \right) - {b}\lambda /{{t}_0}{\text{exp}}\left( { - \lambda {x}/{{t}_0}} \right)} \right]{\text{cos}}\left( {\lambda {y}/{{t}_0}} \right), \hfill \\ \end{split}$$

(16)

$$\begin{split} {E_y} = & - \partial {\varphi _1}\left( {x,y} \right)/\partial y - {\rm d}{\varphi _0}\left( {\text{y}} \right)/{\rm d}y \\ = & \lambda /{{t}_0}\left[ {{a\text{exp}}\left( {\lambda {x}/{{t}_0}} \right) + {b}\lambda /{{t}_0}{\text{exp}}\left( { - \lambda {x}/{{t}_0}} \right)} \right]{\text{sin}}\left( {\lambda {\text{y}}/{{t}_0}} \right) \\ & - 2B{{V}_{\rm t}}\text{tan}\left( {B{y}/{{t}_0}} \right)/{{t}_{0.}}\end{split}$$

(17)

3.2 Calculation of drain current

Using Kane’s model for the BTBT generation rate of carriers, the tunneling current of the proposed device is calculated analytically, which can be written as

$${I_{\rm {DS}}} = q{t_{\rm s}}{L_{\rm t}}{W_{\rm {ch}}}A{\bar E^{2.5}}{\rm{exp}}\left( { - \frac{B}{{\bar E}}} \right),$$

(18)

where W_ch is the channel width of the proposed device, A and B are the tunneling parameters, which are A = 4 × 10¹⁴ cm⁻¹² V⁻⁵² s⁻¹ and B = 1.9 × 10⁷ V/cm^[30]. Moreover, $\bar E$ is the average electric field expressed as $\bar E = {E_{\rm g}}/\left( {q{L_{\rm t}}} \right)$ , and L_t is the shortest tunneling length. At the point L_t, the surface potential will reach E_g/q. Therefore, inserting this value into Eq. (2), we can obtain the expression about L_t, which is expressed as

$${L_{\rm t}} = \frac{{{{\rm{t}}_0}}}{\lambda }{\rm ln}\frac{{\left[ {\left( {{V_{\rm s}} + {E_{\rm g}}/q - {{\rm{\varphi }}_0}\left( {{t_0}} \right)} \right)/\cos \lambda } \right] + \sqrt {{{\left[ {\left( {{V_{\rm s}} + {E_{\rm g}}/q - {\varphi _0}\left( {{t_0}} \right)} \right)/\cos \lambda } \right]}^2} - 4{ab}} }}{{2{a}}}.$$

(19)

4. Results and discussion

The TCAD device simulator Silvaco Atlas is used in this paper, and the models are used as follows: non-local band-to-band tunneling model (btbt), Lombardi mobility model (cvt), Shockley-Read-Hall recombination models (srh), and gap narrowing model (bgn). Moreover, a ferroelectric model from Miller has been implanted to simulate the effects about high dielectric constants, polarization and hysteresis of the ferroelectric material. The remnant polarization of PZT material^[21] is taken as 0.4 μC/cm², saturation polarization as 0.5 μC/cm², and critical electrical field as 0.1 MV/cm in the simulation. It is noteworthy that there are different remnant polarization, saturation polarization and critical electrical field for different ferroelectric materials (such as PZT, SBT, Si:HfO₂) and ferroelectric materials with different thickness (such as 20, 15, and 10 nm of Si:HfO₂)^[26]. However, if it is not easy to obtain the relationship between the thickness of ferroelectric material and the polarization and coercive field, it seems to be reasonable that authors study the effects of the ferroelectric material thickness on the performance of the device under the fixed polarization and coercive field conditions^{[31, 32]}. In other words, we will not consider the effects of the thickness of the ferroelectric materials on the polarization and coercive field.

4.1 Potential model validation

The surface potential of NC DG TFET with SBT material for different V_gs is shown in Fig. 3. It is clear that the calculated results agree well with the simulated results. However, some errors at the source-channel and drain-channel junctions can be found, this is due to the fact that the analytical model ignores the voltage drop across the source and drain regions assumption.

Fig. 4(a) shows the surface potential of the NC DG TFET with different ferroelectric materials and the conventional DG TFET without ferroelectric material layer at V_gs = 1 V and V_ds = 1 V. The typical ferroelectric materials are chosen according to Ref. [29]. It can be found that the surface potential of NC DG TFET is much steeper than that of the conventional DG TFET. This is due to the fact that NC amplifies the internal voltage when the device is operated in the on-state. As a result, it enhances the electric field at the tunneling junction, and reduces the tunneling energy barrier width. Moreover, from Fig. 4(a), it can also be found that the surface potential induced by different ferroelectric materials is slightly different. This is due to the fact that the difference of the total gate capacitance with different FE materials is very small. According to Eq. (6), the surface potential distribution is different, but the difference of the surface potential ${\varphi _0}\left( {{t_0}} \right)$ with different FE material is also very small under the given conditions. Similarly, Fig. 4(b) shows the curve of the surface potential of the proposed device with SBT material for different t_f. Under the given conditions, the difference of the surface potential ${\varphi _0}\left( {{t_0}} \right)$ with SBT material for different thicknesses is also very small. However, when the thickness of FE layer is larger, such as t_f = 100 nm, the total gate capacitance for the proposed device with SBT as FE material will change obviously. Therefore, the surface potential distribution is different because the gate capacitance and surface potential induced by different thickness of ferroelectric material are different.

Fig. 5 shows the lateral electric field for both the simulation and analytical model at V_gs = 1 V and V_ds = 1 V. It can be found that NC DG TFET yields 26.5% improvement in the lateral electric field at the tunnel junction as compared to its counterpart conventional DG TFET. The larger electric field at the tunnel junction can reduce the tunneling energy barrier width, consequently, an enhanced on-current can be obtained.

4.2 Drain current model validation

For quantitative comparison, L_t of the proposed TFET for three ferroelectric materials is shown in Fig. 6(a), which are extracted from Eq. (19). The vertical axis is used for logarithmic coordinates. It can be found that NC DG TFET with SBT material has a slightly lower L_t under the same bias conditions. Fig. 6(b) shows L_t as a function of t_f for three ferroelectric materials, NC DG TFET with SBT material can obtain the minimum L_t among three conditions.

The I_on of the proposed TFET extracted from the analytical model for different t_f is illustrated in Fig. 7, where I_on is defined as the drain current when V_gs and V_ds reach 1 V. It is observed that NC DG TFET with SBT material can obtain the largest On-state current among three ferroelectric materials for any given t_f. Moreover, I_on increases as t_f increases, this is due to the fact that the ferroelectric gate dielectric can also enhance gate controllability over the channel and improve the total gate capacitance. The total gate capacitance (C_eq) of the proposed device can be derived as $1/{C_{\rm {eq}}} = 1/{C_{\rm {in}}} + 1/{C_{\rm {fe}}}$ . The effective oxide thickness (t_eq) is expressed as ${t_{\rm {eq}}} = {t_{\rm {in}}} + 2{t_{\rm f}}u$ as the higher-order terms in Eq. (3) are neglected. Due to u < 0 in the ferroelectric layer, the value of t_eq is lower than that of t_in, so the ferroelectric layer can boost gate controllability over the channel due to the NC effect. Moreover, t_eq decreases with t_f increases, so I_on increases. Therefore, the NC effect in ferroelectric TFETs can solve the lower on-state current of the TFET_on increases. Therefore, the NC effect in ferroelectric TFETs can solve the lower on-state current of the TFET.

The On–Off current ( ${I_{\rm {on}}}/{I_{\rm {off}}}$ ) ratio is an important parameter for digital circuit designing. In this work, I_off is defined as the drain current when V_gs reaches 0 V, at constant V_ds = 1.0 V. As increasing t_f, ${I_{\rm {on}}}/{I_{\rm {off}}}$ is also increased. Moreover, the proposed TFET with SBT material has the largest value of ${I_{\rm {on}}}/{I_{\rm {off}}}$ among the three materials for any given t_f, as shown in Fig. 8.

5. Conclusions

An analytical model taking into account the effects of the channel mobile charge carriers for the NC DG TFET is developed, to analyze the device performances, such as surface potential, electric field, the shortest tunneling length, on-state current, and on–off current ratio. The potential model is widely applied to some other device structures, such as NC gate-all-around (GAA) TFETs, NC silicon-on-insulator (SOI) TFETs, and so on. Furthermore, the on-state current of NC DG TFET increases in magnitude as the thickness of ferroelectric layer increases due to the reduced shortest tunneling length. The impacts of different ferroelectric material variation over the on-state current and the on–off current ratio have also been captured and explained, the results show that the device with SBT material can obtain the largest on-state current and on–off current ratio. The research results provide an incentive for further study and experimental verification.