Citation: |
Shashi Bala, Mamta Khosla. Design and simulation of nanoscale double-gate TFET/tunnel CNTFET[J]. Journal of Semiconductors, 2018, 39(4): 044001. doi: 10.1088/1674-4926/39/4/044001
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S S B la, M Khosla. Design and simulation of nanoscale double-gate TFET/tunnel CNTFET[J]. J. Semicond., 2018, 39(4): 044001. doi: 10.1088/1674-4926/39/4/044001.
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Design and simulation of nanoscale double-gate TFET/tunnel CNTFET
DOI: 10.1088/1674-4926/39/4/044001
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Abstract
A double-gate tunnel field-effect transistor (DG tunnel FET) has been designed and investigated for various channel materials such as silicon (Si), gallium arsenide (GaAs), alminium gallium arsenide (AlxGa1−xAs) and CNT using a nano ViDES Device and TCAD SILVACO ATLAS simulator. The proposed devices are compared on the basis of inverse subthreshold slope (SS), ION/IOFF current ratio and leakage current. Using Si as the channel material limits the property to reduce leakage current with scaling of channel, whereas the AlxGa1−xAs based DG tunnel FET provides a better ION/IOFF current ratio (2.51 × 106) as compared to other devices keeping the leakage current within permissible limits. The performed silmulation of the CNT based channel in the double-gate tunnel field-effect transistor using the nano ViDES shows better performace for a sub-threshold slope of 29.4 mV/dec as the channel is scaled down. The proposed work shows the potential of the CNT channel based DG tunnel FET as a futuristic device for better switching and high retention time, which makes it suitable for memory based circuits. -
References
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