J. Semicond. > 2018, Volume 39 > Issue 5 > 055002
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SEMICONDUCTOR INTEGRATED CIRCUITS

Design and implementation of quadrature bandpass sigma–delta modulator used in low-IF RF receiver

Binjie Ge, Yan Li, Hang Yu and Xiaoxing Feng

+ Author Affiliations

 Corresponding author: Yan Li, Email: liyan@szu.edu.cn

DOI: 10.1088/1674-4926/39/5/055002

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Abstract: This paper presents the design and implementation of quadrature bandpass sigma–delta modulator. A pole movement method for transforming real sigma–delta modulator to a quadrature one is proposed by detailed study of the relationship of noise-shaping center frequency and integrator pole position in sigma–delta modulator. The proposed modulator uses sampling capacitor sharing switched capacitor integrator, and achieves a very small feedback coefficient by a series capacitor network, and those two techniques can dramatically reduce capacitor area. Quantizer output-dependent dummy capacitor load for reference voltage buffer can compensate signal-dependent noise that is caused by load variation. This paper designs a quadrature bandpass Sigma-Delta modulator for 2.4 GHz low IF receivers that achieve 69 dB SNDR at 1 MHz BW and −1 MHz IF with 48 MHz clock. The chip is fabricated with SMIC 0.18 μm CMOS technology, it achieves a total power current of 2.1 mA, and the chip area is 0.48 mm2.

Key words: quadrature, bandpass pole-movement, sigma–delta image-rejection



[1]
Razavi B. RF microelectronics. 2nd ed. Pearson Education, Inc, 2012
[2]
Crols J, Steyaert S J. Low-IF topologies for high-performance analog front ends of fully integrated receivers. IEEE Trans Circuits Syst II, 1998, 45(3): 269 doi: 10.1109/82.664233
[3]
Cui F L. Mixer and image-rejection circuit analysis and design in Bluetooth transceiver. PhD Thesis, Fudan University, 2004
[4]
Xu Y, Zhang Z H, Chi B Y, et al. A 5-/20-MHz BW reconfigurable quadrature bandpass CT ΔΣ ADC with antipole-splitting opamp and digital I/Q calibration. IEEE Trans Very Large Scale Integr (VLSI) Syst, 2016, 24(1): 234
[5]
Zhang J F, Xu Y, Zhang Z H, et al. A 10-b fourth-order quadrature bandpass continuous-time ΣΔ modulator with 33-MHz bandwidth for a dual-channel GNSS receiver. IEEE Trans Microwave Theory Tech, 2017, 65(4): 1303 doi: 10.1109/TMTT.2017.2662378
[6]
Li B, Pun K P. A high image-rejection sc quadrature bandpass DSM for low-IF receivers. IEEE Trans Circuits Syst I, 2014, 61(1): 92 doi: 10.1109/TCSI.2013.2268588
[7]
Allen M, Marttila J, Valkama M. Wideband quadrature sigma-delta A/D conversion for cognitive radio - reconfigurable design and digital mirror-frequency suppression. Vehicular Technology Conference (VTC Fall), 2013: 1090
[8]
Martin K W. Complex signal processing is not complex. IEEE Trans Circuits Syst I, 2004, 51(9): 1823 doi: 10.1109/TCSI.2004.834522
[9]
Pavan S, Schreier R, Temes G. Understanding delta-sigma data converters. 2nd ed. John Wiley & Sons, Inc, 2016
[10]
Neitola M. Loop filter design and optimization for quadrature delta–sigma converters. IEEE European Conference on Circuit Theory and Design, 2015: 24
[11]
Jantzi S A, Martin K W, Sedra A S. Quadrature bandpass modulator for digital radio. IEEE J Solid-State Circuits, 1997, 32(12): 1935 doi: 10.1109/4.643651
[12]
Ge B J, Wang X A, Zhang X, et al. Sigma-delta modulator modeling analysis and design. J Semicond, 2010, 31(9): 095003 doi: 10.1088/1674-4926/31/9/095003
[13]
Ge B J, Wang X A, Zhang X, et al. Study and analysis of coefficient mismatch in a MASH21 sigma-delta modulator. J Semicond, 2010, 31(1): 015007 doi: 10.1088/1674-4926/31/1/015007
[14]
Razavi B. Design of analog CMOS intergrated circuits. 2nd ed. McGraw-Hill Education, 2016
[15]
Philips K. A 4.4 mW 76 dB complex ADC for bluetooth receivers. IEEE ISSCC, 2003: 64
[16]
Atac A, Liao L, Wang Y, et al. A 1.7 mW quadrature bandpass ΔΣ ADC with 1 MHz bandwidth and 60 dB DR at 1 MHz IF. IEEE International Symposium on Circuits & Systems, 2013, 1035(10): 1039
Fig. 1.  Low-IF receiver with quadrature bandpass sigma–delta modulator.

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Fig. 2.  1st order lowpass sigma–delta modulator.

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Fig. 3.  Signal flow graph of complex integrator.

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Fig. 4.  Complex integrator realized by cross-coupled real integrators.

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Fig. 5.  Proposed quadrature bandpass sigma–delta modulator.

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Fig. 6.  PSD of proposed modulator in MATLAB modeling.

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Fig. 7.  (a) Real 3rd order sigma–delta modulator. (b) Quadrature bandpass sigma–delta modulator.

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Fig. 8.  PH1 Phase network of zero feedback.

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Fig. 9.  PH2 Phase network of zero feedback.

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Fig. 10.  Dummy capacitor load for reference voltage buffer.

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Fig. 11.  Fully differential input comparator.

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Fig. 12.  (Color online) Photograph of the fabricated modulator in transceiver.

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Fig. 13.  (Color online) PCB test board of proposed modulator.

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Fig. 14.  (Color online) PSD of post simulation and testing results.

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Fig. 15.  Two tones test PSD of proposed modulator.

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Table 1.   Pole movement.

Pole name Real-SDM Complex-SDM Image-Delta
Real-Pole 1 0.9914 − j0.1305 0.1305
Complex-Pole1 0.9989 + j0.0468 0.9842 − j0.084 0.1308
Complex-Pole2 0.9989 − j0.0468 0.9964 − j0.1768 0.1300
DownLoad: CSV

Table 2.   Modulator coefficient values.

Name Ideal Real Name Ideal Real
a1 0.1 1/8 c1 0.3561 2/8
a2 0.2425 2/8 c2 0.3778 3/8
a3 0.3561 3/8 c3 5.5 5.5
b1 0.044 1/16 g 0.006 1/240
DownLoad: CSV

Table 3.   Opamp design specifications.

Parameter 1st opamp 2nd opamp 3rd opamp
Slew rate (MV/s) 120 60 60
DC gain (dB) 50 52 52
GBW (MHz) 550 280 280
Von (mV) 40 60 60
Power current (μA) 490 240 240
DownLoad: CSV

Table 4.   Modulator capacitor value.

Cap 1st integrator 2nd integrator 3rd integrator Zero cap
CS 2C0 2C0 3C0 CZ3 = 1C0
CIQ 4C0 1C0 1C0
CFB 2C0 CS share CS share CZ3 = 28C0
CI 32C0 8C0 8C0 CZ3 = 1C0
DownLoad: CSV

Table 5.   Test results and comparison.

Parameter Ref. [15] Ref. [16] This work
Bandwidth (MHz) 1 1 1
IF (MHz) 0.5 1 −1
fs (MHz) 64 32 48
Modulator 5th CT 3rd CT 3rd SC
DR (dB) 76 60 70
SNDRpeak (dB) 75.5 58.6 > 69
Image rejection (dB) > 47 44.6 ---
IM3 distortion (dBc) < −82 −49 < −58
Power (mA) 2.44 @ 1.8 V 1.42 @ 1.2 V 2.1 @ 1.8 V
Technology (μm) 0.18 0.13 0.18
Area (mm2) 0.22 0.62 0.48
DownLoad: CSV
[1]
Razavi B. RF microelectronics. 2nd ed. Pearson Education, Inc, 2012
[2]
Crols J, Steyaert S J. Low-IF topologies for high-performance analog front ends of fully integrated receivers. IEEE Trans Circuits Syst II, 1998, 45(3): 269 doi: 10.1109/82.664233
[3]
Cui F L. Mixer and image-rejection circuit analysis and design in Bluetooth transceiver. PhD Thesis, Fudan University, 2004
[4]
Xu Y, Zhang Z H, Chi B Y, et al. A 5-/20-MHz BW reconfigurable quadrature bandpass CT ΔΣ ADC with antipole-splitting opamp and digital I/Q calibration. IEEE Trans Very Large Scale Integr (VLSI) Syst, 2016, 24(1): 234
[5]
Zhang J F, Xu Y, Zhang Z H, et al. A 10-b fourth-order quadrature bandpass continuous-time ΣΔ modulator with 33-MHz bandwidth for a dual-channel GNSS receiver. IEEE Trans Microwave Theory Tech, 2017, 65(4): 1303 doi: 10.1109/TMTT.2017.2662378
[6]
Li B, Pun K P. A high image-rejection sc quadrature bandpass DSM for low-IF receivers. IEEE Trans Circuits Syst I, 2014, 61(1): 92 doi: 10.1109/TCSI.2013.2268588
[7]
Allen M, Marttila J, Valkama M. Wideband quadrature sigma-delta A/D conversion for cognitive radio - reconfigurable design and digital mirror-frequency suppression. Vehicular Technology Conference (VTC Fall), 2013: 1090
[8]
Martin K W. Complex signal processing is not complex. IEEE Trans Circuits Syst I, 2004, 51(9): 1823 doi: 10.1109/TCSI.2004.834522
[9]
Pavan S, Schreier R, Temes G. Understanding delta-sigma data converters. 2nd ed. John Wiley & Sons, Inc, 2016
[10]
Neitola M. Loop filter design and optimization for quadrature delta–sigma converters. IEEE European Conference on Circuit Theory and Design, 2015: 24
[11]
Jantzi S A, Martin K W, Sedra A S. Quadrature bandpass modulator for digital radio. IEEE J Solid-State Circuits, 1997, 32(12): 1935 doi: 10.1109/4.643651
[12]
Ge B J, Wang X A, Zhang X, et al. Sigma-delta modulator modeling analysis and design. J Semicond, 2010, 31(9): 095003 doi: 10.1088/1674-4926/31/9/095003
[13]
Ge B J, Wang X A, Zhang X, et al. Study and analysis of coefficient mismatch in a MASH21 sigma-delta modulator. J Semicond, 2010, 31(1): 015007 doi: 10.1088/1674-4926/31/1/015007
[14]
Razavi B. Design of analog CMOS intergrated circuits. 2nd ed. McGraw-Hill Education, 2016
[15]
Philips K. A 4.4 mW 76 dB complex ADC for bluetooth receivers. IEEE ISSCC, 2003: 64
[16]
Atac A, Liao L, Wang Y, et al. A 1.7 mW quadrature bandpass ΔΣ ADC with 1 MHz bandwidth and 60 dB DR at 1 MHz IF. IEEE International Symposium on Circuits & Systems, 2013, 1035(10): 1039

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    Received: 25 July 2017 Revised: 12 December 2017 Online: Accepted Manuscript: 13 January 2018Uncorrected proof: 24 January 2018Published: 01 May 2018

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      Article Navigation >  Journal of Semiconductors  > 2018  >  39(5): 055002
      Binjie Ge, Yan Li, Hang Yu, Xiaoxing Feng. Design and implementation of quadrature bandpass sigma–delta modulator used in low-IF RF receiver[J]. Journal of Semiconductors, 2018, 39(5): 055002. doi: 10.1088/1674-4926/39/5/055002 ****B J Ge, Y Li, H Yu, X X Feng. Design and implementation of quadrature bandpass sigma–delta modulator used in low-IF RF receiver[J]. J. Semicond., 2018, 39(5): 055002. doi: 10.1088/1674-4926/39/5/055002.
      Citation:
      Binjie Ge, Yan Li, Hang Yu, Xiaoxing Feng. Design and implementation of quadrature bandpass sigma–delta modulator used in low-IF RF receiver[J]. Journal of Semiconductors, 2018, 39(5): 055002. doi: 10.1088/1674-4926/39/5/055002 ****
      B J Ge, Y Li, H Yu, X X Feng. Design and implementation of quadrature bandpass sigma–delta modulator used in low-IF RF receiver[J]. J. Semicond., 2018, 39(5): 055002. doi: 10.1088/1674-4926/39/5/055002.
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      Design and implementation of quadrature bandpass sigma–delta modulator used in low-IF RF receiver

      DOI: 10.1088/1674-4926/39/5/055002

      • College of Computer Science & Software Engineering, Shenzhen University, Shenzhen 518060, China

      Funds:

      Project supported by the National Natural Science Foundation of China (Nos. 61471245, U1201256), the Guangdong Province Foundation (No. 2014B090901031), and the Shenzhen Foundation (Nos. JCYJ20160308095019383, JSGG20150529160945187).

      More Information
      • Corresponding author: Email: liyan@szu.edu.cn
      • Received Date: 2017-07-25
      • Revised Date: 2017-12-12
      • Published Date: 2018-05-01

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