Low-temperature metal–oxide thin-film transistor technologies for implementing flexible electronic circuits and systems

Runxiao Shi; Tengteng Lei; Zhihe Xia; Man Wong

doi:10.1088/1674-4926/44/9/091601

J. Semicond. > 2023, Volume 44 > Issue 9 > 091601

REVIEWS

Low-temperature metal–oxide thin-film transistor technologies for implementing flexible electronic circuits and systems

Runxiao Shi^§, Tengteng Lei^§, Zhihe Xia and Man Wong

+ Author Affiliations

State Key Laboratory of Advanced Displays and Optoelectronics and Technologies, Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, Hong Kong, China
^§Runxiao Shi and Tengteng Lei contributed equally to this work and should be considered as co-first authors.

Author Bio:

Runxiao Shi received his BE degree from Southeast University in 2017 and ME degree from Waseda University in 2018. He is currently working toward a PhD degree with the Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology. His research interests include flexible indium-gallium-zinc–oxide thin-film transistors and circuits based on metal–oxide TFTs.

Tengteng Lei got her BS degree from Sun Yat-sen University in 2017 and MS degree from Peking University in 2020. She is currently a PhD student at the State Key Laboratory of Advanced Displays and Optoelectronics Technologies of The Hong Kong University of Science and Technology under the supervision of Prof. Man Wong. Her research interests include metal–oxide thin-film transistors, thin-film integrated circuit design, and tactile sensor arrays.

Zhihe Xia received a PhD degree from the Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, Hong Kong, in 2019. His current research interests include novel metal–oxide thin-film transistors with advanced devices and flexible electronics.

Man Wong received a PhD degree in electrical engineering from the Center for Integrated Systems, Stanford University, Palo Alto, CA, USA. Since 1992, he has been a faculty member at the Department of Electrical and Electronic Engineering of The Hong Kong University of Science and Technology, Hong Kong.

Corresponding author: Man Wong, eemwong@ust.hk

DOI: 10.1088/1674-4926/44/9/091601

Abstract: Here we review two 300 °C metal–oxide (MO) thin-film transistor (TFT) technologies for the implementation of flexible electronic circuits and systems. Fluorination-enhanced TFTs for suppressing the variation and shift of turn-on voltage (V_ON), and dual-gate TFTs for acquiring sensor signals and modulating V_ON have been deployed to improve the robustness and performance of the systems in which they are deployed. Digital circuit building blocks based on fluorinated TFTs have been designed, fabricated, and characterized, which demonstrate the utility of the proposed low-temperature TFT technologies for implementing flexible electronic systems. The construction and characterization of an analog front-end system for the acquisition of bio-potential signals and an active-matrix sensor array for the acquisition of tactile images have been reported recently.

Key words: flexible electronics, metal–oxide semiconductor, thin-film transistor, dual gate, fluorination, analog front-end system, sensors

1. Introduction

Besides their deployment in a flat-panel information display^[1], low-temperature thin-film transistors (TFTs) have been used to construct flexible electronic systems such as radio-frequency identification tags^[2], bio-sensor interface circuits^[3] and microprocessors^[4], etc. Offering relatively higher field-effect mobility ( ${\mu }_{\mathrm{F}\mathrm{E}}$ ) than that of the TFTs built on hydrogenated amorphous silicon and significantly lower off-state currents than that of those built on low-temperature polysilicon, TFTs built on metal–oxide (MO) semiconductors such as indium-gallium-zinc oxide (IGZO)^[5] and indium-tin-zinc oxide (ITZO)^[6] have been intensely investigated.

Donor-species, such as hydrogen (H)^{[7, 8]} or those derived from oxygen deficiency^{[9, 10]}, when residing in excess in the channel region of a TFT lead to variation and negative shift of the turn-on voltage ( ${V}_{\mathrm{O}\mathrm{N}}$ )^[11] of a TFT. These often result in degradation in the performance, such as a reduced noise margin^[12], attenuated gain^[13] and reduced output voltage swing^[14] of a circuit constructed of the TFTs. While thermal annealing is deployed to suppress the population of such species^[10], the accessible conditions of a heat-treatment process are constrained by the material properties of the flexible substrate on which the TFTs are constructed. For a popular substrate such as polyimide (PI), these constraints include a maximum process temperature of below 400 °C that further reduces with increasing transparency of the PI; a mismatch between the thermal expansion coefficient of the PI and that of its glass carrier substrate leading to possible cracking of the PI after an extended heat-treatment^[15]; and introduction into a TFT of H originating from the decomposition of hydrocarbon or hydroxyl species in the PI during its laser lift-off (LLO) from its carrier substrate^[16], etc.

A series of studies addressing issues concerning the design and construction of circuits and systems based on MO TFTs are reviewed here. The topics include how the variation of TFT electrical parameters affects the performance of a circuit; how fluorination is deployed to suppress such variation and enhance the stability of a TFT^[17]; and how dual-gate (DG) TFTs, with at least a part of its channel region sandwiched between two parallel gate electrodes, allow the modulation of the effective ${V}_{\mathrm{O}\mathrm{N}}$ referred to as one gate by a bias applied on the other. Given the inevitable variation of the electrical parameters of TFTs, DG TFTs can be deployed as signal-acquisition devices in a sensor array and applied in a scheme for mitigating the detrimental effects of such variation. Finally, the construction and characterization of an integrated analog front-end circuit built using a single-gate (SG) IGZO TFT technology and an active-matrix tactile sensor array built using a DG ITZO TFT technology are reviewed.

2. Low-temperature MO TFT technologies

2.1 Fluorination-enhanced MO TFT

On the starting 0.5-mm-thick glass carrier substrate coated with a 10-μm-thick PI, the preparation of MO TFTs (Fig. 1(a)) starts with the formation of a stack of buffer layers consisting of 200-nm-thick silicon nitride (SiN_y) under 300-nm-thick silicon oxide (SiO_x), where both are deposited at 300 °C in a plasma-enhanced chemical vapor deposition (PECVD) system. A 100-nm-thick molybdenum (Mo) layer is sputtered and patterned in an aqueous mixture of phosphoric, nitric, and acetic acids to form the bottom gate (BG) electrodes. A 75-nm-thick PECVD SiO_x on a 50-nm-thick PECVD SiN_y stacked dielectric is next formed at 300 °C. A 20-nm-thick amorphous IGZO active layer is then sputtered at room temperature using an In₂O₃ : Ga₂O₃ : ZnO = 1 : 1 : 1 target in an atmosphere of 90% argon (Ar) and 10% oxygen (O₂). Some of the samples are next treated in a tetrafluoromethane (CF₄) plasma for 10 min in the PECVD chamber at 300 °C to form IGZO:F^[9], i.e. fluorinated IGZO. Active islands are patterned by etching in a 1/2000 hydrofluoric acid solution before a 300-nm-thick PECVD SiO_x etch-stop (ES) layer is deposited. The contact holes to the BG and source/drain (S/D) regions are opened in an inductively coupled plasma etcher running a sulfur hexafluoride chemistry. Electrodes are constructed of sputtered and patterned stacks of 300-nm-thick aluminum (Al) on 50-nm-thick Mo. During a subsequent annealing process at 300 °C in O₂ for 4 h, portions of the active island covered by the gas-impermeable Al/Mo electrodes become the conductive S/D regions, while the portion covered by the exposed gas-permeable SiO_x becomes the channel region of a TFT^[18]. LLO to separate the TFT-carrying PI from the carrier substrate is accomplished using a 308 nm XeCl excimer laser irradiated through the substrate.

Fig. 1. (Color online) (a) A schematic cross-section of an IGZO or IGZO:F TFT. (b) Comparison of the measured transfer characteristics of IGZO:F and IGZO TFTs with W = 10 µm and L decreasing from 50 to 2 µm. (c) Comparison of the measured transfer characteristics of IGZO:F and IGZO TFTs before and after LLO. (d) Measured statistical distributions of the

DownLoad: Full-Size Img PowerPoint

The transfer characteristics, i.e. the dependence of the drain current ( ${I}_{\mathrm{D}}$ ) on the gate-to-source voltage ( ${V}_{\mathrm{G}\mathrm{S}}$ ), of two sets of IGZO and IGZO:F TFTs are shown in (b). Each set consists of 7 TFTs, with a channel width ( $W$ ) of 10 μm and channel length ( $L$ ) reducing from 50 to 2 μm. Defined as the ${V}_{\mathrm{G}\mathrm{S}}$ required to induce an ${I}_{\mathrm{D}}$ of 1 pA at a drain-to-source voltage ( ${V}_{\mathrm{D}\mathrm{S}}$ ) of 0.5 V, the ${V}_{\mathrm{O}\mathrm{N}}$ of the IGZO:F TFTs with different $L$ cluster around 0 V, while that of an IGZO TFT shifts negatively with decreasing $L$ –thus exhibiting significant apparent short-channel effects (SCE). The reduced vulnerability of IGZO:F TFTs to apparent SCE is attributed to the suppressed population of donor-species in a fluorinated channel.

Comparisons are made of the performance of TFTs before and after LLO. It can be seen in (c) that the characteristics of the IGZO:F TFT remain unchanged, while those of the IGZO TFT exhibit a negative shift in ${V}_{\mathrm{O}\mathrm{N}}$ and the appearance of a weak hump after LLO. The statistical variations of the ${V}_{\mathrm{O}\mathrm{N}}$ of IGZO:F and IGZO TFTs with L = 50, 20 and 10 μm before and after the LLO are shown in (d). Ten TFTs are measured for each $L$ . The negative shift in ${V}_{\mathrm{O}\mathrm{N}}$ and the corresponding standard deviation of the ${V}_{\mathrm{O}\mathrm{N}}$ of the IGZO:F TFTs are significantly smaller than those of the IGZO TFTs. The degradation of the performance of the IGZO TFTs after LLO is attributed to the generation of donor-species, such as water molecules evolving from the PI or H generated during the LLO, and their subsequent diffusion into the channel region. The improved performance of the IGZO:F TFT is consistent with their reported resilience against H-induced degradation^[7].

2.2 DG MO TFT

The evolution of the cross-section of a DG ITZO TFT through its process of construction is shown in Fig. 2. On a similar substrate as the 0.5-mm-thick glass carrier substrate coated with a 10-μm-thick PI, a stack of buffer layers consisting of 200-nm-thick SiN_y under 300-nm-thick SiO_x was deposited at 300 °C in a PECVD system. A 100-nm-thick Mo layer is sputtered and patterned as the BG electrode before the PECVD of a bottom gate-insulator (GI) stack consisting of 75-nm-thick SiO_x on 50-nm-thick SiN_y. Following a 2-h furnace anneal in O₂ at 300 °C, a 20-nm-thick ITZO active layer is sputtered in an atmosphere of 60% Ar and 40% O₂. After patterning the ITZO layer to form an active island, a 100-nm-thick SiO_x is deposited as the top GI. Following another furnace anneal at 300 °C for 6 h in O₂, a 150-nm-thick Mo is sputter-deposited and patterned to form the top-gate electrode (TG) before the deposition of a 200-nm-thick SiO_x. This is followed by a furnace anneal for 8 h in O₂ at 250 °C. Formation of the S/D regions self-aligned to the edges of the TG is accomplished by exposure to an O₂ plasma^[19], while the portion of the active island covered by the TG retains its semiconducting property and becomes the channel region. Contact holes to access the TG, S/D, and BG layers are subsequently opened before a stack of 200-nm-thick Al on 150-nm-thick Mo is deposited and patterned to form the electrodes.

Fig. 2. (Color online) The fabrication process of SG and DG ITZO TFTs.

DownLoad: Full-Size Img PowerPoint

The transfer characteristics of 9 SG ITZO TFTs with $W$ / $L$ of 20/10 µm/µm, randomly selected over a 4-inch substrate, are shown in Fig. 3(a). The “modulating gate (MG)” of a DG TFT is the BG or the TG connected to a fixed bias, the remaining gate connected to a variable bias is called the “operating gate (OG)”. Shown in (b) and (c) are the ${I}_{\mathrm{D}}$ vs. OG voltage (i.e. ${V}_{\mathrm{B}\mathrm{G}}$ or ${V}_{\mathrm{T}\mathrm{G}}$ ) curves of six DG TFTs with $W/L$ of 100/10 µm/µm at MG voltage (i.e. ${V}_{\mathrm{T}\mathrm{G}}$ or ${V}_{\mathrm{B}\mathrm{G}}$ ) of −5, 0, and 5 V. Shown in (d) is the statistical distribution of the extracted threshold voltage ( ${V}_{\mathrm{T}\mathrm{H}}$ ) of the SG ITZO TFTs, where ${V}_{\mathrm{T}\mathrm{H}}$ is defined as the gate voltage required to generate an ${I}_{\mathrm{D}}$ of 1 nA at ${V}_{\mathrm{D}\mathrm{S}}=5$ V. The mean ( ${\bar{V}}_{\mathrm{T}\mathrm{H}}$ ) and standard deviation ( $\sigma \left({V}_{\mathrm{T}\mathrm{H}}\right)$ ) of ${V}_{\mathrm{T}\mathrm{H}}$ are respectively −3.5 and 0.6 V. For the DG ITZO TFTs with TG as OG and BG as MG, the corresponding ${\bar{V}}_{\mathrm{T}\mathrm{H}}$ and $\sigma \left({V}_{\mathrm{T}\mathrm{H}}\right)$ values shown in (e) are respectively −4.2 and 0.3 V at ${V}_{\mathrm{B}\mathrm{G}}=0$ V. Exhibited in (f) is the statistical distribution of ${V}_{\mathrm{T}\mathrm{H}}$ of the DG ITZO TFTs with BG as the OG and TG as the MG. The ${\bar{V}}_{\mathrm{T}\mathrm{H}}$ and σ( ${V}_{\mathrm{T}\mathrm{H}}$ ) are respectively −4.3 and 0.3 V at ${V}_{\mathrm{T}\mathrm{G}}=0$ V. Clearly, both SG and DG ITZO TFTs exhibit non-uniformity in their electrical parameters.

Fig. 3. (Color online) Transfer characteristics of (a) SG TFTs, (b) DG TFTs with BG as the MG and TG as the OG, and (c) DG TFTs with TG as the MG and BG as the OG; extracted

${V}_{\mathrm{T}\mathrm{H}}$ of (d) SG TFTs, (e) DG TFTs with BG as the MG and TG as the OG, and (f) DG TFTs with TG as the MG and BG as the OG.

DownLoad: Full-Size Img PowerPoint

3. Circuit building blocks

Converting an n-bit digital input to one of a maximum of 2ⁿ unique digital outputs, a binary decoder is used to demonstrate the utility of fluorination in improving circuit performance^[17]. Shown in (a) is the gate-level schematic, consisting of 2 inverters (INV) and 4 NOR gates, and the truth table of a 2-4 decoder with 2 inputs ( ${I}_{0}$ and ${I}_{1}$ ) and 4 outputs ( ${O}_{0}$ , ${O}_{1}$ , ${O}_{2}$ and ${O}_{3}$ ). Designed in the “pseudo-CMOS” style^[20], the TFT-level schematics and the truth tables of INV and NOR are shown respectively in (b) and (c). ${V}_{\mathrm{S}\mathrm{S}}$ is an additional voltage source required by the pseudo-CMOS design style to ensure full swing of the output signal from the ground $GND$ to the supply voltage ${V}_{\mathrm{D}\mathrm{D}}$ . A photograph of a fabricated decoder on the PI is shown in Fig. 4(d).

Fig. 4. (Color online) Fluorination-enhanced 2-4 decoder^[17]. (a) Gate-level schematic and truth table of a 2-4 decoder. (b) TFT-level circuit diagram and truth table of an INV. (c) TFT-level circuit diagram and truth table of a NOR. (d) A photograph of a fabricated 2-4 decoder on PI. (e) Measured VTCs of 2-4 decoders fabricated using IGZO:F TFTs. (f) Measured VTCs of 2-4 decoders fabricated using IGZO TFTs. (g) Simulated VTCs of ideal implementation with the same

${V}_{\mathrm{O}\mathrm{N}}$ ~ 0 V for all TFTs. (h) Implementation with

DownLoad: Full-Size Img PowerPoint

With ${V}_{\mathrm{D}\mathrm{D}}$ , ${V}_{\mathrm{S}\mathrm{S}}$ and $GND$ set respectively to 5, 12 and 0 V, the voltage-transfer characteristics (VTCs) of decoders implemented using IGZO:F and IGZO TFTs are shown respectively in (e) and (f), where the voltage levels corresponding to the respective logic inputs ${I}_{i}:i=0,\mathrm{ }1$ and logic outputs ${O}_{j}:j=0,\mathrm{ }1,\mathrm{ }2,\mathrm{ }3$ are denoted by ${V}_{{I}_{i}}$ and ${V}_{{O}_{j}}$ . Logic states “0” and “1” correspond respectively to the voltage levels of $GND$ and ${V}_{\mathrm{D}\mathrm{D}}$ . It can be seen from (e) that the decoder built using IGZO:F TFTs operates in a manner close to that of an ideal decoder, i.e, only one output exhibits logic “1”, while the rest exhibits logic “0” for any given input configuration. However, the behavior of the decoder shown in (f) build using IGZO TFTs deviates from that of an ideal decoder: a) When ${V}_{{I}_{1}}$ = 0 V and ${V}_{{I}_{0}}$ = 5 V, ${V}_{{O}_{1}}$ fails to reach 5 V and ${V}_{{O}_{0}}$ fails to reach 0 V. b) When ${V}_{{I}_{1}}$ = 5 V, ${V}_{{O}_{0}}$ is well above 0 V. c) ${V}_{{O}_{3}}$ fail to reach 5 V, when ${V}_{{I}_{0}}$ = ${V}_{{I}_{1}}$ = 5 V.

The simulated VTCs of a 2–4 decoder when ${V}_{{I}_{1}}$ = 0 V are shown in (g) and (h). The measured VTCs of a decoder built using IGZO TFTs are closer to the simulated VTCs when a negative shift of ${V}_{\mathrm{O}\mathrm{N}}$ is imposed. By suppressing the negative shift of ${V}_{\mathrm{O}\mathrm{N}}$ of TFTs, fluorination improves the performance of the decoder. Consequently, the measured VTCs of a decoder built using IGZO:F TFTs is much closer to the simulated VTCs shown in the ideal case when variation is suppressed and all the TFTs in the decoder have the same ${V}_{\mathrm{O}\mathrm{N}}$ .

4. Demonstration flexible electronic systems

4.1 Analog front-end system

Based on the fluorinated SG IGZO TFT technology, an analog front-end (AFE) system for the acquisition of bio-potential signals is designed, fabricated, and characterized^[21]. The architecture of the AFE system is shown in Fig. 5(a), consisting of three sub-systems of (Ⅰ) bias-filters to remove the half cell-potential generated at the contacts between the sensing electrodes and the skin, and to bias the bio-potential to match the operating point of (Ⅱ) a differential amplifier deployed to magnify the bio-potential signal and to suppress the common-mode noise, and (Ⅲ) a notch filter to suppress the power line noise. A fabricated AFE system on the PI placed on the thenar muscle of a hand is shown in (b). IGZO TFTs serve not only as active devices but are also deployed to realize physically small resistors with high resistance. Additionally, the combination of a thermally induced IGZO conductor and the thin gate insulator allows the realization of a physically small capacitor with a large capacitance per unit area. It is the combination of these small components in the bias and notch filters that makes it possible to realize an AFE with a small footprint of ~11 mm². With two of the three electrodes connected to the two inputs ${V}_{\mathrm{I}\mathrm{N}+}$ and ${V}_{\mathrm{I}\mathrm{N}-}$ , and the remaining one to the ground node of the AFE, in-vitro measurements of electromyogram (EMG) and electrocardiogram (ECG) have been performed. The respective electrode connections and the traces of the EMG and ECG are shown in Figs. 5(c) and 5(d).

Fig. 5. (Color online) An AFE system for the acquisition of bio-potential signals. (a) System architecture. (b) PI carrying AFE systems placed on the thenar muscle of a hand. In-vitro measurements of (c) EMG and (d) ECG^[21]. Copyright 2023 Wiley.

DownLoad: Full-Size Img PowerPoint

4.2 Tactile sensor array

Using thin-film piezoelectric polyvinylidene fluoride (PVDF) as a sensing medium, an active-matrix tactile sensor array^[22] has been implemented using the DG ITZO TFT technology. Shown in (a) is the circuit schematic of an in-pixel amplifier consisting of a DG driving TFT M1, a diode-connected SG load TFT M2, and a switching TFT M3. One gate of M1 is employed as an input gate terminal to receive the input signal ${V}_{\mathrm{I}}$ and the other gate is employed as an MG terminal biased at a voltage ${V}_{\mathrm{B}}$ . The corresponding amplified voltage is contained in the output signal ${V}_{\mathrm{O}}$ . The timing diagram associated with the active-matrix addressing of the tactile sensor array is shown in (b). With ${V}_{\mathrm{D}\mathrm{D}}$ = 10 V, ${V}_{\mathrm{L}\mathrm{L}}$ = 4 V and a constant ${V}_{\mathrm{B}}$ = 8 V ((c)), the dependence of the voltage gain ${A}_{\mathrm{V}}$ on ${V}_{\mathrm{I}}$ for 40 in-pixels amplifiers are characterized and shown in (d). Exhibited in (e) are the corresponding ${A}_{\mathrm{V}}$ at ${V}_{\mathrm{I}}$ = 0 V, showing a relatively wide range of 1.5 V/V between −0.5 and −2 V/V.

Fig. 6. (Color online) DG ITZO TFT-based in-pixel amplifiers w/ and w/o provision for compensation of TFT parameter variation: (a) circuit schematic and (b) timing diagram; (c) distribution of MG voltage

${V}_{\mathrm{B}}$ for 40 pixel circuits w/ and w/o compensation; (d) dependance of

${A}_{\mathrm{V}}$ on

${V}_{\mathrm{I}}$ and (e) distribution of

${A}_{\mathrm{V}}$ at

${V}_{\mathrm{I}}=0$ V for 40 amplifiers w/o compensation. In-pixel amplifiers w/ provision for compensation of TFT parameter variation: (f) circuit schematic and (g) timing diagram; (h) microscope image of a tactile pixel and (i) photograph of a 16

$\times$ 16 active-matrix tactile sensor array; (j) dependance of

${A}_{\mathrm{V}}$ on

${V}_{\mathrm{I}}$ and (k) distribution of

${A}_{\mathrm{V}}$ at

DownLoad: Full-Size Img PowerPoint

The circuit schematic and timing diagrams of an in-pixel amplifier are shown in Figs. 6(f) and 6(g), allowing the application of a compensation scheme. Shown respectively in Figs. 6(h) and (i) are photographs of a 625 × 625 µm tactile pixel and a 16 × 16 tactile sensor array with compensation. With a global compensation signal CMP, the compensation and signal-acquisition scheme operate in two stages: Stage 1 is the compensation phase for setting ${V}_{\mathrm{B}}={V}_{\mathrm{O}}$ and Stage 2 is the acquisition phase for acquiring the signal ${V}_{\mathrm{I}}$ . During Stage 1, the threshold voltage of M1 in every pixel is modulated by switching on M4 and M5 to allow M1 to be consistently biased in the saturation mode. During Stage 2, the compensated ${V}_{\mathrm{B}}$ generated in Stage 1 is stored on the capacitor ${C}_{\mathrm{S}}$ by switching off M4 and M5. The compensated ${V}_{\mathrm{B}}$ shown in (c) ranges between 6.6 and 7.5 V, reflecting the non-uniformity of TFT parameters. The resulting ${A}_{\mathrm{V}}\approx$ −2 V/V varies over a much tighter range of 0.1 V/V, as shown in Figs. 6(j) and 6(k).

A constant ${V}_{\mathrm{B}}$ of 8 V for an uncompensated array and the self-biased ${V}_{\mathrm{B}}$ extracted from a compensated array are shown respectively in (a) and (b). ${V}_{\mathrm{B}}$ in Fig. 7(b) gradually increases from the upper right to the lower left corner of the array, reflecting a systematic trend of the variation of the parameters of the TFTs across the corresponding diagonal of the array. Obtained with the arrays loaded with a letter stamp “O”, respective tactile images w/o and w/ compensation are displayed in Figs. 7(c) and (d). Sharper edges corresponding to better uniformity are observed for the compensated image exhibited in (d). The tactile images acquired using a smaller 8 $\times$ 8 tactile sensor array^[23] are shown in Fig. 7(e), with the mass of the 3D-printed letter and number stamps in the range of dozens of milligrams.

Fig. 7. (Color online) MG voltage

${V}_{\mathrm{B}}$ distribution over a 16

$\times$ 16 tactile sensor array (a) w/o and (b) w/ compensation^[22]; tactile images from arrays (c) w/o and (d) w/ compensation when loaded with a letter stamp “O”; (e) tactile images acquired from an 8 × 8 tactile sensor array^[23]. Copyright 2022 and 2023 IEEE.

DownLoad: Full-Size Img PowerPoint

5. Future perspectives

While oxygen deficiency is reported to be responsible for the generation of carrier donors in the S/D regions of a SG TFT processed at 400 °C, a recent kinetic model^[8] suggests the generation of such donors should be negligible at 300 °C. Consequently, the mechanism responsible for the formation of the conductive S/D regions at 300 °C needs to be clarified. Furthermore, the principle behind the O₂-plasma induced activation of the S/D regions in DG TFTs is currently unknown and needs to be investigated.

A schematic system diagram of a more capable bio-potential acquisition system is shown in Fig. 8. In addition to the bias filter, differential amplifier and notch filter are reviewed in the present work, an analog-to-digital converter (ADC) for converting the acquired bio-potential from an analog signal to a digital signal, a wireless module for transmission of the converted signal to a terminal for further data processing and display, and a power management module could also be integrated.

Fig. 8. (Color online) A schematic system diagram of a more capable bio-potential acquisition system on a flexible substrate.

DownLoad: Full-Size Img PowerPoint

A bionic “smart” system consisting of a tactile sensor array and an artificial neural network is shown in Fig. 9. The flexible tactile sensor array based on the integration of PVDF film and DG MO TFTs could be applied to health monitoring, such as pulse-wave measurement. Near-sensor and in-sensor neuromorphic computing were achieved by the artificial neural network which could enable flexible electronic skin with bionic tactile perception.

Fig. 9. (Color online) Flexible tactile sensor array integrated with an artificial neural network as a bionic “smart” system.

DownLoad: Full-Size Img PowerPoint

6. Conclusion

300 °C MO TFT technologies based both on IGZO and ITZO for the implementation of flexible electronic systems have been reviewed. Fluorination has been reported to suppress the variation and shift of ${V}_{\mathrm{O}\mathrm{N}}$ , and DG TFTs have been deployed to modulate the ${V}_{\mathrm{O}\mathrm{N}}$ and to acquire sensor signals. Both are found to improve the robustness and performance of the systems in which they are deployed. Demonstrating the utility of the TFT technologies to the construction of flexible electronic systems, an analog front-end system for the acquisition of bio-potential signals and an active-matrix sensor array for the acquisition of tactile images have been reported.

Acknowledgment

This work was supported by Grant RGC 16215720 from the Science and Technology Program of Shenzhen under JCYJ20200109140601691, Grant GHP/018/21SZ from the Innovation and Technology Fund jointly with Grant SGDX20211123145404006 from the Science and Technology Program of Shenzhen and in part by Fundamental and Applied Fundamental Research Fund of Guangdong Province 2021B1515130001. The devices were fabricated at The Nanosystem Fabrication Facility (NFF) of The Hong Kong University of Science and Technology.

References

[1]	Zhu Y, He Y L, Jiang S S, et al. Indium–gallium–zinc–oxide thin-film transistors: Materials, devices, and applications. J Semicond, 2021, 42, 031101 doi: 10.1088/1674-4926/42/3/031101
[2]	Myny K, Lai Y C, Papadopoulos N, et al. A flexible ISO14443-a compliant 7.5mW 128b metal-oxide NFC barcode tag with direct clock division circuit from 13.56MHz carrier. 2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, 258 doi: 10.1109/ISSCC.2017.7870359
[3]	Fuketa H, Yoshioka K, Shinozuka Y, et al. 1µm-thickness 64-channel surface electromyogram measurement sheet with 2V organic transistors for prosthetic hand control. 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 2013, 104 doi: 10.1109/ISSCC.2013.6487656
[4]	Biggs J, Myers J, Kufel J, et al. A natively flexible 32-bit Arm microprocessor. Nature, 2021, 595, 532 doi: 10.1038/s41586-021-03625-w
[5]	Hosono H. How we made the IGZO transistor. Nat Electron, 2018, 1, 428 doi: 10.1038/s41928-018-0106-0
[6]	Xia Z H, Lu L, Li J P, et al. Self-aligned elevated-metal metal-oxide thin-film transistors for displays and flexible electronics. 2019 IEEE International Electron Devices Meeting (IEDM), 2020, 8.4. 1 doi: 10.1109/IEDM19573.2019.8993653
[7]	Wang S S, Shi R X, Li J P, et al. Resilience of fluorinated indium-gallium-zinc oxide thin-film transistor against hydrogen-induced degradation. IEEE Electron Device Lett, 2020, 41, 729 doi: 10.1109/LED.2020.2983789
[8]	Wang Y Q, Jiang W, Xie X Y, et al. A kinetic model for the generation and annihilation of thermally induced carrier donors in a semiconducting metal-oxide thin film. Small, 2022, 18, 2203346 doi: 10.1002/smll.202203346
[9]	Lu L, Xia Z H, Li J P, et al. A comparative study on fluorination and oxidation of indium–gallium–zinc oxide thin-film transistors. IEEE Electron Device Lett, 2018, 39, 196 doi: 10.1109/LED.2017.2781700
[10]	Li J P, Lu L, Feng Z Q, et al. An oxidation-last annealing for enhancing the reliability of indium-gallium-zinc oxide thin-film transistors. Appl Phys Lett, 2017, 110, 142102 doi: 10.1063/1.4979649
[11]	Wang S S, Shi R X, Li J P, et al. 24-2: Distinguished student paper: Fluorination for enhancing the resistance of indium-gallium-zinc oxide thin-film transistor against hydrogen-induced degradation. SID Symp Dig Tech Pap, 2020, 51, 347 doi: 10.1002/sdtp.13875
[12]	Myny K. The development of flexible integrated circuits based on thin-film transistors. Nat Electron, 2018, 1, 30 doi: 10.1038/s41928-017-0008-6
[13]	Spijkman M J, Myny K, Smits E C P, et al. Dual-gate thin-film transistors, integrated circuits and sensors. Adv Mater, 2011, 23, 3231 doi: 10.1002/adma.201101493
[14]	Lei T, Shao L L, Zheng Y Q, et al. Low-voltage high-performance flexible digital and analog circuits based on ultrahigh-purity semiconducting carbon nanotubes. Nat Commun, 2019, 10, 1 doi: 10.1038/s41467-018-07882-8
[15]	Liu F Y, Liu Z H, Gao S Y, et al. Polyimide film with low thermal expansion and high transparency by self-enhancement of polyimide/SiC nanofibers net. RSC Adv, 2018, 8, 19034 doi: 10.1039/C8RA02479K
[16]	Yung K C, Zeng D W, Yue T M. XPS investigation of Upilex-S polyimide ablated by 355 nm Nd: YAG laser irradiation. Appl Surf Sci, 2001, 173, 193 doi: 10.1016/S0169-4332(00)00884-9
[17]	Shi R X, Wang S S, Xia Z H, et al. Fluorinated metal-oxide thin-film transistors for circuit implementation on a flexible substrate. IEEE J Flex Electron, 2022, 1, 58 doi: 10.1109/JFLEX.2021.3140044
[18]	Lu L, Li J P, Kwok H S, et al. High-performance and reliable elevated-metal metal-oxide thin-film transistor for high-resolution displays. 2016 IEEE International Electron Devices Meeting (IEDM), 2017, 32.2. 1 doi: 10.1109/IEDM.2016.7838526
[19]	Xie X, Chen K, Zhou Z, et al. Conductive indium-tin-zinc-oxide formed using an oxygen plasma treatment through a silicon oxide cover layer. in Digest Tech. Papers SID'23 Conference, 2023.
[20]	Huang T C, Fukuda K, Lo C M, et al. Pseudo-CMOS: A design style for low-cost and robust flexible electronics. IEEE Trans Electron Devices, 2011, 58, 141 doi: 10.1109/TED.2010.2088127
[21]	Shi R X, Liu X C, Lei T T, et al. An integrated analog front-end system on flexible substrate for the acquisition of bio-potential signals. Adv Sci, 2023, 10, 2207683 doi: 10.1002/advs.202207683
[22]	Lei T, Hu Y, Xie X, et al. An active-matrix piezoelectric tactile sensor array with in-pixel amplifier and non-uniformity compensation. in Digest Tech. Papers Transducers'23 Conference, 2023.
[23]	Lei T T, Hu Y S, Wong M. Active-matrix tactile sensor array based on the monolithic integration of pvdf and dual-gate transistors. 2022 IEEE 35th International Conference on Micro Electro Mechanical Systems Conference (MEMS), 2022, 71 doi: 10.1109/MEMS51670.2022.9699743

DownLoad: Full-Size Img PowerPoint

Fig. 2. (Color online) The fabrication process of SG and DG ITZO TFTs.

DownLoad: Full-Size Img PowerPoint

Fig. 3. (Color online) Transfer characteristics of (a) SG TFTs, (b) DG TFTs with BG as the MG and TG as the OG, and (c) DG TFTs with TG as the MG and BG as the OG; extracted

${V}_{\mathrm{T}\mathrm{H}}$ of (d) SG TFTs, (e) DG TFTs with BG as the MG and TG as the OG, and (f) DG TFTs with TG as the MG and BG as the OG.

DownLoad: Full-Size Img PowerPoint

${V}_{\mathrm{O}\mathrm{N}}$ ~ 0 V for all TFTs. (h) Implementation with

DownLoad: Full-Size Img PowerPoint

${V}_{\mathrm{B}}$ for 40 pixel circuits w/ and w/o compensation; (d) dependance of

${A}_{\mathrm{V}}$ on

${V}_{\mathrm{I}}$ and (e) distribution of

${A}_{\mathrm{V}}$ at

$\times$ 16 active-matrix tactile sensor array; (j) dependance of

${A}_{\mathrm{V}}$ on

${V}_{\mathrm{I}}$ and (k) distribution of

${A}_{\mathrm{V}}$ at

DownLoad: Full-Size Img PowerPoint

Fig. 7. (Color online) MG voltage

${V}_{\mathrm{B}}$ distribution over a 16

DownLoad: Full-Size Img PowerPoint

Fig. 8. (Color online) A schematic system diagram of a more capable bio-potential acquisition system on a flexible substrate.

DownLoad: Full-Size Img PowerPoint

Fig. 9. (Color online) Flexible tactile sensor array integrated with an artificial neural network as a bionic “smart” system.

DownLoad: Full-Size Img PowerPoint

[1]	Zhu Y, He Y L, Jiang S S, et al. Indium–gallium–zinc–oxide thin-film transistors: Materials, devices, and applications. J Semicond, 2021, 42, 031101 doi: 10.1088/1674-4926/42/3/031101
[2]	Myny K, Lai Y C, Papadopoulos N, et al. A flexible ISO14443-a compliant 7.5mW 128b metal-oxide NFC barcode tag with direct clock division circuit from 13.56MHz carrier. 2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, 258 doi: 10.1109/ISSCC.2017.7870359
[3]	Fuketa H, Yoshioka K, Shinozuka Y, et al. 1µm-thickness 64-channel surface electromyogram measurement sheet with 2V organic transistors for prosthetic hand control. 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 2013, 104 doi: 10.1109/ISSCC.2013.6487656
[4]	Biggs J, Myers J, Kufel J, et al. A natively flexible 32-bit Arm microprocessor. Nature, 2021, 595, 532 doi: 10.1038/s41586-021-03625-w
[5]	Hosono H. How we made the IGZO transistor. Nat Electron, 2018, 1, 428 doi: 10.1038/s41928-018-0106-0
[6]	Xia Z H, Lu L, Li J P, et al. Self-aligned elevated-metal metal-oxide thin-film transistors for displays and flexible electronics. 2019 IEEE International Electron Devices Meeting (IEDM), 2020, 8.4. 1 doi: 10.1109/IEDM19573.2019.8993653
[7]	Wang S S, Shi R X, Li J P, et al. Resilience of fluorinated indium-gallium-zinc oxide thin-film transistor against hydrogen-induced degradation. IEEE Electron Device Lett, 2020, 41, 729 doi: 10.1109/LED.2020.2983789
[8]	Wang Y Q, Jiang W, Xie X Y, et al. A kinetic model for the generation and annihilation of thermally induced carrier donors in a semiconducting metal-oxide thin film. Small, 2022, 18, 2203346 doi: 10.1002/smll.202203346
[9]	Lu L, Xia Z H, Li J P, et al. A comparative study on fluorination and oxidation of indium–gallium–zinc oxide thin-film transistors. IEEE Electron Device Lett, 2018, 39, 196 doi: 10.1109/LED.2017.2781700
[10]	Li J P, Lu L, Feng Z Q, et al. An oxidation-last annealing for enhancing the reliability of indium-gallium-zinc oxide thin-film transistors. Appl Phys Lett, 2017, 110, 142102 doi: 10.1063/1.4979649
[11]	Wang S S, Shi R X, Li J P, et al. 24-2: Distinguished student paper: Fluorination for enhancing the resistance of indium-gallium-zinc oxide thin-film transistor against hydrogen-induced degradation. SID Symp Dig Tech Pap, 2020, 51, 347 doi: 10.1002/sdtp.13875
[12]	Myny K. The development of flexible integrated circuits based on thin-film transistors. Nat Electron, 2018, 1, 30 doi: 10.1038/s41928-017-0008-6
[13]	Spijkman M J, Myny K, Smits E C P, et al. Dual-gate thin-film transistors, integrated circuits and sensors. Adv Mater, 2011, 23, 3231 doi: 10.1002/adma.201101493
[14]	Lei T, Shao L L, Zheng Y Q, et al. Low-voltage high-performance flexible digital and analog circuits based on ultrahigh-purity semiconducting carbon nanotubes. Nat Commun, 2019, 10, 1 doi: 10.1038/s41467-018-07882-8
[15]	Liu F Y, Liu Z H, Gao S Y, et al. Polyimide film with low thermal expansion and high transparency by self-enhancement of polyimide/SiC nanofibers net. RSC Adv, 2018, 8, 19034 doi: 10.1039/C8RA02479K
[16]	Yung K C, Zeng D W, Yue T M. XPS investigation of Upilex-S polyimide ablated by 355 nm Nd: YAG laser irradiation. Appl Surf Sci, 2001, 173, 193 doi: 10.1016/S0169-4332(00)00884-9
[17]	Shi R X, Wang S S, Xia Z H, et al. Fluorinated metal-oxide thin-film transistors for circuit implementation on a flexible substrate. IEEE J Flex Electron, 2022, 1, 58 doi: 10.1109/JFLEX.2021.3140044
[18]	Lu L, Li J P, Kwok H S, et al. High-performance and reliable elevated-metal metal-oxide thin-film transistor for high-resolution displays. 2016 IEEE International Electron Devices Meeting (IEDM), 2017, 32.2. 1 doi: 10.1109/IEDM.2016.7838526
[19]	Xie X, Chen K, Zhou Z, et al. Conductive indium-tin-zinc-oxide formed using an oxygen plasma treatment through a silicon oxide cover layer. in Digest Tech. Papers SID'23 Conference, 2023.
[20]	Huang T C, Fukuda K, Lo C M, et al. Pseudo-CMOS: A design style for low-cost and robust flexible electronics. IEEE Trans Electron Devices, 2011, 58, 141 doi: 10.1109/TED.2010.2088127
[21]	Shi R X, Liu X C, Lei T T, et al. An integrated analog front-end system on flexible substrate for the acquisition of bio-potential signals. Adv Sci, 2023, 10, 2207683 doi: 10.1002/advs.202207683
[22]	Lei T, Hu Y, Xie X, et al. An active-matrix piezoelectric tactile sensor array with in-pixel amplifier and non-uniformity compensation. in Digest Tech. Papers Transducers'23 Conference, 2023.
[23]	Lei T T, Hu Y S, Wong M. Active-matrix tactile sensor array based on the monolithic integration of pvdf and dual-gate transistors. 2022 IEEE 35th International Conference on Micro Electro Mechanical Systems Conference (MEMS), 2022, 71 doi: 10.1109/MEMS51670.2022.9699743

1	Implementation of sub-100 nm vertical channel-all-around (CAA) thin-film transistor using thermal atomic layer deposited IGZO channel Yuting Chen, Xinlv Duan, Xueli Ma, Peng Yuan, Zhengying Jiao, et al. Journal of Semiconductors, 2024, 45(7): 072301. doi: 10.1088/1674-4926/24010032
2	Indium–gallium–zinc–oxide thin-film transistors: Materials, devices, and applications Ying Zhu, Yongli He, Shanshan Jiang, Li Zhu, Chunsheng Chen, et al. Journal of Semiconductors, 2021, 42(3): 031101. doi: 10.1088/1674-4926/42/3/031101
3	Inkjet printed large-area flexible circuits: a simple methodology for optimizing the printing quality Tao Cheng, Youwei Wu, Xiaoqin Shen, Wenyong Lai, Wei Huang, et al. Journal of Semiconductors, 2018, 39(1): 015001. doi: 10.1088/1674-4926/39/1/015001
4	Recent advances in flexible and wearable organic optoelectronic devices Hong Zhu, Yang Shen, Yanqing Li, Jianxin Tang Journal of Semiconductors, 2018, 39(1): 011011. doi: 10.1088/1674-4926/39/1/011011
5	Graphene-based flexible and wearable electronics Tanmoy Das, Bhupendra K. Sharma, Ajit K. Katiyar, Jong-Hyun Ahn Journal of Semiconductors, 2018, 39(1): 011007. doi: 10.1088/1674-4926/39/1/011007
6	Hybrid functional microfibers for textile electronics and biosensors Bichitra Nanda Sahoo, Byungwoo Choi, Jungmok Seo, Taeyoon Lee Journal of Semiconductors, 2018, 39(1): 011009. doi: 10.1088/1674-4926/39/1/011009
7	Materials and applications of bioresorbable electronics Xian Huang Journal of Semiconductors, 2018, 39(1): 011003. doi: 10.1088/1674-4926/39/1/011003
8	Oxide-based thin film transistors for flexible electronics Yongli He, Xiangyu Wang, Ya Gao, Yahui Hou, Qing Wan, et al. Journal of Semiconductors, 2018, 39(1): 011005. doi: 10.1088/1674-4926/39/1/011005
9	Dual material gate doping-less tunnel FET with hetero gate dielectric for enhancement of analog/RF performance Sunny Anand, R.K. Sarin Journal of Semiconductors, 2017, 38(2): 024001. doi: 10.1088/1674-4926/38/2/024001
10	ZnO_1-xTe_x and ZnO_1-xS_x semiconductor alloys as competent materials for opto-electronic and solar cell applications:a comparative analysis Utsa Das, Partha P. Pal Journal of Semiconductors, 2017, 38(8): 082001. doi: 10.1088/1674-4926/38/8/082001
11	The impact of gate misalignment on the analog performance of a dual-material double gate junctionless transistor S. Intekhab Amin, R. K. Sarin Journal of Semiconductors, 2015, 36(9): 094001. doi: 10.1088/1674-4926/36/9/094001
12	Effects of interface trap density on the electrical performance of amorphous InSnZnO thin-film transistor Yongye Liang, Kyungsoo Jang, S. Velumani, Cam Phu Thi Nguyen, Junsin Yi, et al. Journal of Semiconductors, 2015, 36(2): 024007. doi: 10.1088/1674-4926/36/2/024007
13	Progress in complementary metal-oxide-semiconductor silicon photonics and optoelectronic integrated circuits Hongda Chen, Zan Zhang, Beiju Huang, Luhong Mao, Zanyun Zhang, et al. Journal of Semiconductors, 2015, 36(12): 121001. doi: 10.1088/1674-4926/36/12/121001
14	In situ TEM/SEM electronic/mechanical characterization of nano material with MEMS chip Yuelin Wang, Tie Li, Xiao Zhang, Hongjiang Zeng, Qinhua Jin, et al. Journal of Semiconductors, 2014, 35(8): 081001. doi: 10.1088/1674-4926/35/8/081001
15	The effects of electron irradiation on the optical properties of the organic semiconductor polypyrrole J. V. Thombare, M. C. Rath, S. H. Han, V. J. Fulari Journal of Semiconductors, 2013, 34(9): 093001. doi: 10.1088/1674-4926/34/9/093001
16	Design of an analog front-end for ambulatory biopotential measurement systems Wang Jiazhen, Xu Jun, Zheng Lirong, Ren Junyan Journal of Semiconductors, 2010, 31(10): 105004. doi: 10.1088/1674-4926/31/10/105004
17	Comparison of electron transmittances and tunneling currents in an anisotropic TiN_x/HfO₂/SiO₂/p-Si(100) metal–oxide–semiconductor (MOS) capacitor calculated using exponential- and Airy-wavefunction app Fatimah A. Noor, Mikrajuddin Abdullah, Sukirno, Khairurrijal Journal of Semiconductors, 2010, 31(12): 124002. doi: 10.1088/1674-4926/31/12/124002
18	Optical and electrical properties of N-doped ZnO and fabrication of thin-film transistors Zhu Xiaming, Wu Huizhen, Wang Shuangjiang, Zhang Yingying, Cai Chunfeng, et al. Journal of Semiconductors, 2009, 30(3): 033001. doi: 10.1088/1674-4926/30/3/033001
19	Design and Analysis of Analog Front-End of Passive RFID Transponders Hu Jianyun, He Yan, Min Hao Chinese Journal of Semiconductors , 2006, 27(6): 999-1005.
20	Electronic Structure of Semiconductor Nanocrystals Li Jingbo, Wang Linwang, Wei Suhuai Chinese Journal of Semiconductors , 2006, 27(2): 191-196.

1.	He, J., Wang, S., Han, R. et al. Wide Detection Range Flexible Pressure Sensors Based on 3D Interlocking Structure TPU/ZnO NWs. Advanced Functional Materials, 2025, 35(15): 2418791. doi:10.1002/adfm.202418791
2.	Wang, H., Zhou, M., Jia, X. et al. Recent progress on artificial intelligence-enhanced multimodal sensors integrated devices and systems. Journal of Semiconductors, 2025, 46(1): 011610. doi:10.1088/1674-4926/24090041
3.	Xu, Q., Huang, F., Sun, X. et al. Progress in Wearable Bionic Sensors for Biomedical Applications. Macromolecular Chemistry and Physics, 2025. doi:10.1002/macp.202400500
4.	Li, Y., Qiu, Z., Kan, H. et al. A Human-Computer Interaction Strategy for An FPGA Platform Boosted Integrated “Perception-Memory” System Based on Electronic Tattoos and Memristors. Advanced Science, 2024, 11(39): 2402582. doi:10.1002/advs.202402582
5.	Sun, X., Guo, X., Gao, J. et al. E-Skin and Its Advanced Applications in Ubiquitous Health Monitoring. Biomedicines, 2024, 12(10): 2307. doi:10.3390/biomedicines12102307
6.	Zhang, L., Zhou, R., Ma, W. et al. Junction Piezotronic Transistor Arrays Based on Patterned ZnO Nanowires for High-Resolution Tactile and Photo Mapping. Sensors, 2024, 24(15): 4775. doi:10.3390/s24154775
7.	Zhu, G., Chen, Z., Zhang, M. et al. Reliability of indium-tin-zinc-oxide thin-film transistors under dynamic drain voltage stress. Applied Physics Letters, 2024, 125(2): 023505. doi:10.1063/5.0213509
8.	Encinas-Terán, A., Pineda-León, H.A., Gómez-Colín, M.R. et al. Synthesis and Characterization of a Semiconductor Diodic Bilayer PbS/CdS Made by the Chemical Bath Deposition Technique. ACS Omega, 2024, 9(23): 24321-24332. doi:10.1021/acsomega.3c10051
9.	Zhu, G., Zhang, M., Lu, L. et al. Hot Carrier Degradation Reduction in Metal Oxide Thin-Film Transistors by Implementing a Lightly Doped Drain-Like Structure. IEEE Electron Device Letters, 2024, 45(9): 1602-1605. doi:10.1109/LED.2024.3424473
10.	Alboteanu, G., Ya'akobovitz, A. Exceptionally large fracture strength and stretchability of 2D ReS2 and ReSe2. Nanoscale, 2023, 16(7): 3454-3461. doi:10.1039/d3nr03670g
11.	Kwok, H.-S., Fan, Z. Preface to Special Issue on Advanced Optoelectronic and Electronic Devices toward Future Displays. Journal of Semiconductors, 2023, 44(9): 090101. doi:10.1088/1674-4926/44/9/090101

Search

GET CITATION

R X Shi, T T Lei, Z H Xia, M Wong. Low-temperature metal–oxide thin-film transistor technologies for implementing flexible electronic circuits and systems[J]. J. Semicond, 2023, 44(9): 091601. doi: 10.1088/1674-4926/44/9/091601

Export: BibTex EndNote

Article Metrics

Article views: 1295 Times PDF downloads: 165 Times Cited by: 11 Times

History

Received: 23 April 2023 Revised: 06 June 2023 Online: Accepted Manuscript: 15 August 2023Corrected proof: 18 August 2023Uncorrected proof: 21 August 2023Published: 10 September 2023

Article Navigation > Journal of Semiconductors > 2023 > 44(9): 091601

Runxiao Shi, Tengteng Lei, Zhihe Xia, Man Wong. Low-temperature metal–oxide thin-film transistor technologies for implementing flexible electronic circuits and systems[J]. Journal of Semiconductors, 2023, 44(9): 091601. doi: 10.1088/1674-4926/44/9/091601 ****R X Shi, T T Lei, Z H Xia, M Wong. Low-temperature metal–oxide thin-film transistor technologies for implementing flexible electronic circuits and systems[J]. J. Semicond, 2023, 44(9): 091601. doi: 10.1088/1674-4926/44/9/091601

Citation:

PDF( 9047 KB)

Low-temperature metal–oxide thin-film transistor technologies for implementing flexible electronic circuits and systems

DOI: 10.1088/1674-4926/44/9/091601

State Key Laboratory of Advanced Displays and Optoelectronics and Technologies, Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, Hong Kong, China

More Information

Runxiao Shi：received his BE degree from Southeast University in 2017 and ME degree from Waseda University in 2018. He is currently working toward a PhD degree with the Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology. His research interests include flexible indium-gallium-zinc–oxide thin-film transistors and circuits based on metal–oxide TFTs
Tengteng Lei：got her BS degree from Sun Yat-sen University in 2017 and MS degree from Peking University in 2020. She is currently a PhD student at the State Key Laboratory of Advanced Displays and Optoelectronics Technologies of The Hong Kong University of Science and Technology under the supervision of Prof. Man Wong. Her research interests include metal–oxide thin-film transistors, thin-film integrated circuit design, and tactile sensor arrays
Zhihe Xia：received a PhD degree from the Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, Hong Kong, in 2019. His current research interests include novel metal–oxide thin-film transistors with advanced devices and flexible electronics
Man Wong：received a PhD degree in electrical engineering from the Center for Integrated Systems, Stanford University, Palo Alto, CA, USA. Since 1992, he has been a faculty member at the Department of Electrical and Electronic Engineering of The Hong Kong University of Science and Technology, Hong Kong
Corresponding author: eemwong@ust.hk
Received Date: 2023-04-23
Revised Date: 2023-06-06

Available Online: 2023-08-15

Abstract

Abstract

Here we review two 300 °C metal–oxide (MO) thin-film transistor (TFT) technologies for the implementation of flexible electronic circuits and systems. Fluorination-enhanced TFTs for suppressing the variation and shift of turn-on voltage (V_ON), and dual-gate TFTs for acquiring sensor signals and modulating V_ON have been deployed to improve the robustness and performance of the systems in which they are deployed. Digital circuit building blocks based on fluorinated TFTs have been designed, fabricated, and characterized, which demonstrate the utility of the proposed low-temperature TFT technologies for implementing flexible electronic systems. The construction and characterization of an analog front-end system for the acquisition of bio-potential signals and an active-matrix sensor array for the acquisition of tactile images have been reported recently.
- flexible electronics,
- metal–oxide semiconductor,
- thin-film transistor,
- dual gate,
- fluorination,
- analog front-end system,
- sensors

^§Runxiao Shi and Tengteng Lei contributed equally to this work and should be considered as co-first authors.

FullText(HTML)

1. Introduction

Besides their deployment in a flat-panel information display^[1], low-temperature thin-film transistors (TFTs) have been used to construct flexible electronic systems such as radio-frequency identification tags^[2], bio-sensor interface circuits^[3] and microprocessors^[4], etc. Offering relatively higher field-effect mobility ( ${\mu }_{\mathrm{F}\mathrm{E}}$ ) than that of the TFTs built on hydrogenated amorphous silicon and significantly lower off-state currents than that of those built on low-temperature polysilicon, TFTs built on metal–oxide (MO) semiconductors such as indium-gallium-zinc oxide (IGZO)^[5] and indium-tin-zinc oxide (ITZO)^[6] have been intensely investigated.

Donor-species, such as hydrogen (H)^{[7, 8]} or those derived from oxygen deficiency^{[9, 10]}, when residing in excess in the channel region of a TFT lead to variation and negative shift of the turn-on voltage ( ${V}_{\mathrm{O}\mathrm{N}}$ )^[11] of a TFT. These often result in degradation in the performance, such as a reduced noise margin^[12], attenuated gain^[13] and reduced output voltage swing^[14] of a circuit constructed of the TFTs. While thermal annealing is deployed to suppress the population of such species^[10], the accessible conditions of a heat-treatment process are constrained by the material properties of the flexible substrate on which the TFTs are constructed. For a popular substrate such as polyimide (PI), these constraints include a maximum process temperature of below 400 °C that further reduces with increasing transparency of the PI; a mismatch between the thermal expansion coefficient of the PI and that of its glass carrier substrate leading to possible cracking of the PI after an extended heat-treatment^[15]; and introduction into a TFT of H originating from the decomposition of hydrocarbon or hydroxyl species in the PI during its laser lift-off (LLO) from its carrier substrate^[16], etc.

A series of studies addressing issues concerning the design and construction of circuits and systems based on MO TFTs are reviewed here. The topics include how the variation of TFT electrical parameters affects the performance of a circuit; how fluorination is deployed to suppress such variation and enhance the stability of a TFT^[17]; and how dual-gate (DG) TFTs, with at least a part of its channel region sandwiched between two parallel gate electrodes, allow the modulation of the effective ${V}_{\mathrm{O}\mathrm{N}}$ referred to as one gate by a bias applied on the other. Given the inevitable variation of the electrical parameters of TFTs, DG TFTs can be deployed as signal-acquisition devices in a sensor array and applied in a scheme for mitigating the detrimental effects of such variation. Finally, the construction and characterization of an integrated analog front-end circuit built using a single-gate (SG) IGZO TFT technology and an active-matrix tactile sensor array built using a DG ITZO TFT technology are reviewed.

2. Low-temperature MO TFT technologies

2.1 Fluorination-enhanced MO TFT

On the starting 0.5-mm-thick glass carrier substrate coated with a 10-μm-thick PI, the preparation of MO TFTs (Fig. 1(a)) starts with the formation of a stack of buffer layers consisting of 200-nm-thick silicon nitride (SiN_y) under 300-nm-thick silicon oxide (SiO_x), where both are deposited at 300 °C in a plasma-enhanced chemical vapor deposition (PECVD) system. A 100-nm-thick molybdenum (Mo) layer is sputtered and patterned in an aqueous mixture of phosphoric, nitric, and acetic acids to form the bottom gate (BG) electrodes. A 75-nm-thick PECVD SiO_x on a 50-nm-thick PECVD SiN_y stacked dielectric is next formed at 300 °C. A 20-nm-thick amorphous IGZO active layer is then sputtered at room temperature using an In₂O₃ : Ga₂O₃ : ZnO = 1 : 1 : 1 target in an atmosphere of 90% argon (Ar) and 10% oxygen (O₂). Some of the samples are next treated in a tetrafluoromethane (CF₄) plasma for 10 min in the PECVD chamber at 300 °C to form IGZO:F^[9], i.e. fluorinated IGZO. Active islands are patterned by etching in a 1/2000 hydrofluoric acid solution before a 300-nm-thick PECVD SiO_x etch-stop (ES) layer is deposited. The contact holes to the BG and source/drain (S/D) regions are opened in an inductively coupled plasma etcher running a sulfur hexafluoride chemistry. Electrodes are constructed of sputtered and patterned stacks of 300-nm-thick aluminum (Al) on 50-nm-thick Mo. During a subsequent annealing process at 300 °C in O₂ for 4 h, portions of the active island covered by the gas-impermeable Al/Mo electrodes become the conductive S/D regions, while the portion covered by the exposed gas-permeable SiO_x becomes the channel region of a TFT^[18]. LLO to separate the TFT-carrying PI from the carrier substrate is accomplished using a 308 nm XeCl excimer laser irradiated through the substrate.

Fig. 1. (Color online) (a) A schematic cross-section of an IGZO or IGZO:F TFT. (b) Comparison of the measured transfer characteristics of IGZO:F and IGZO TFTs with W = 10 µm and L decreasing from 50 to 2 µm. (c) Comparison of the measured transfer characteristics of IGZO:F and IGZO TFTs before and after LLO. (d) Measured statistical distributions of the ${V}_{\mathrm{O}\mathrm{N}}$ of IGZO:F and IGZO TFTs before and after LLO^[17]. Copyright 2021 IEEE.

DownLoad: Full-Size Img PowerPoint

The transfer characteristics, i.e. the dependence of the drain current ( ${I}_{\mathrm{D}}$ ) on the gate-to-source voltage ( ${V}_{\mathrm{G}\mathrm{S}}$ ), of two sets of IGZO and IGZO:F TFTs are shown in (b). Each set consists of 7 TFTs, with a channel width ( $W$ ) of 10 μm and channel length ( $L$ ) reducing from 50 to 2 μm. Defined as the ${V}_{\mathrm{G}\mathrm{S}}$ required to induce an ${I}_{\mathrm{D}}$ of 1 pA at a drain-to-source voltage ( ${V}_{\mathrm{D}\mathrm{S}}$ ) of 0.5 V, the ${V}_{\mathrm{O}\mathrm{N}}$ of the IGZO:F TFTs with different $L$ cluster around 0 V, while that of an IGZO TFT shifts negatively with decreasing $L$ –thus exhibiting significant apparent short-channel effects (SCE). The reduced vulnerability of IGZO:F TFTs to apparent SCE is attributed to the suppressed population of donor-species in a fluorinated channel.

Comparisons are made of the performance of TFTs before and after LLO. It can be seen in (c) that the characteristics of the IGZO:F TFT remain unchanged, while those of the IGZO TFT exhibit a negative shift in ${V}_{\mathrm{O}\mathrm{N}}$ and the appearance of a weak hump after LLO. The statistical variations of the ${V}_{\mathrm{O}\mathrm{N}}$ of IGZO:F and IGZO TFTs with L = 50, 20 and 10 μm before and after the LLO are shown in (d). Ten TFTs are measured for each $L$ . The negative shift in ${V}_{\mathrm{O}\mathrm{N}}$ and the corresponding standard deviation of the ${V}_{\mathrm{O}\mathrm{N}}$ of the IGZO:F TFTs are significantly smaller than those of the IGZO TFTs. The degradation of the performance of the IGZO TFTs after LLO is attributed to the generation of donor-species, such as water molecules evolving from the PI or H generated during the LLO, and their subsequent diffusion into the channel region. The improved performance of the IGZO:F TFT is consistent with their reported resilience against H-induced degradation^[7].

2.2 DG MO TFT

The evolution of the cross-section of a DG ITZO TFT through its process of construction is shown in Fig. 2. On a similar substrate as the 0.5-mm-thick glass carrier substrate coated with a 10-μm-thick PI, a stack of buffer layers consisting of 200-nm-thick SiN_y under 300-nm-thick SiO_x was deposited at 300 °C in a PECVD system. A 100-nm-thick Mo layer is sputtered and patterned as the BG electrode before the PECVD of a bottom gate-insulator (GI) stack consisting of 75-nm-thick SiO_x on 50-nm-thick SiN_y. Following a 2-h furnace anneal in O₂ at 300 °C, a 20-nm-thick ITZO active layer is sputtered in an atmosphere of 60% Ar and 40% O₂. After patterning the ITZO layer to form an active island, a 100-nm-thick SiO_x is deposited as the top GI. Following another furnace anneal at 300 °C for 6 h in O₂, a 150-nm-thick Mo is sputter-deposited and patterned to form the top-gate electrode (TG) before the deposition of a 200-nm-thick SiO_x. This is followed by a furnace anneal for 8 h in O₂ at 250 °C. Formation of the S/D regions self-aligned to the edges of the TG is accomplished by exposure to an O₂ plasma^[19], while the portion of the active island covered by the TG retains its semiconducting property and becomes the channel region. Contact holes to access the TG, S/D, and BG layers are subsequently opened before a stack of 200-nm-thick Al on 150-nm-thick Mo is deposited and patterned to form the electrodes.

Fig. 2. (Color online) The fabrication process of SG and DG ITZO TFTs.

DownLoad: Full-Size Img PowerPoint

The transfer characteristics of 9 SG ITZO TFTs with $W$ / $L$ of 20/10 µm/µm, randomly selected over a 4-inch substrate, are shown in Fig. 3(a). The “modulating gate (MG)” of a DG TFT is the BG or the TG connected to a fixed bias, the remaining gate connected to a variable bias is called the “operating gate (OG)”. Shown in (b) and (c) are the ${I}_{\mathrm{D}}$ vs. OG voltage (i.e. ${V}_{\mathrm{B}\mathrm{G}}$ or ${V}_{\mathrm{T}\mathrm{G}}$ ) curves of six DG TFTs with $W/L$ of 100/10 µm/µm at MG voltage (i.e. ${V}_{\mathrm{T}\mathrm{G}}$ or ${V}_{\mathrm{B}\mathrm{G}}$ ) of −5, 0, and 5 V. Shown in (d) is the statistical distribution of the extracted threshold voltage ( ${V}_{\mathrm{T}\mathrm{H}}$ ) of the SG ITZO TFTs, where ${V}_{\mathrm{T}\mathrm{H}}$ is defined as the gate voltage required to generate an ${I}_{\mathrm{D}}$ of 1 nA at ${V}_{\mathrm{D}\mathrm{S}}=5$ V. The mean ( ${\bar{V}}_{\mathrm{T}\mathrm{H}}$ ) and standard deviation ( $\sigma \left({V}_{\mathrm{T}\mathrm{H}}\right)$ ) of ${V}_{\mathrm{T}\mathrm{H}}$ are respectively −3.5 and 0.6 V. For the DG ITZO TFTs with TG as OG and BG as MG, the corresponding ${\bar{V}}_{\mathrm{T}\mathrm{H}}$ and $\sigma \left({V}_{\mathrm{T}\mathrm{H}}\right)$ values shown in (e) are respectively −4.2 and 0.3 V at ${V}_{\mathrm{B}\mathrm{G}}=0$ V. Exhibited in (f) is the statistical distribution of ${V}_{\mathrm{T}\mathrm{H}}$ of the DG ITZO TFTs with BG as the OG and TG as the MG. The ${\bar{V}}_{\mathrm{T}\mathrm{H}}$ and σ( ${V}_{\mathrm{T}\mathrm{H}}$ ) are respectively −4.3 and 0.3 V at ${V}_{\mathrm{T}\mathrm{G}}=0$ V. Clearly, both SG and DG ITZO TFTs exhibit non-uniformity in their electrical parameters.

(Color online) Transfer characteristics of (a) SG TFTs, (b) DG TFTs with BG as the MG and TG as the OG, and (c) DG TFTs with TG as the MG and BG as the OG; extracted ${V}_{\mathrm{T}\mathrm{H}}$ of (d) SG TFTs, (e) DG TFTs with BG as the MG and TG as the OG, and (f) DG TFTs with TG as the MG and BG as the OG.

DownLoad: Full-Size Img PowerPoint

3. Circuit building blocks

Converting an n-bit digital input to one of a maximum of 2ⁿ unique digital outputs, a binary decoder is used to demonstrate the utility of fluorination in improving circuit performance^[17]. Shown in (a) is the gate-level schematic, consisting of 2 inverters (INV) and 4 NOR gates, and the truth table of a 2-4 decoder with 2 inputs ( ${I}_{0}$ and ${I}_{1}$ ) and 4 outputs ( ${O}_{0}$ , ${O}_{1}$ , ${O}_{2}$ and ${O}_{3}$ ). Designed in the “pseudo-CMOS” style^[20], the TFT-level schematics and the truth tables of INV and NOR are shown respectively in (b) and (c). ${V}_{\mathrm{S}\mathrm{S}}$ is an additional voltage source required by the pseudo-CMOS design style to ensure full swing of the output signal from the ground $GND$ to the supply voltage ${V}_{\mathrm{D}\mathrm{D}}$ . A photograph of a fabricated decoder on the PI is shown in Fig. 4(d).

(Color online) Fluorination-enhanced 2-4 decoder^[17]. (a) Gate-level schematic and truth table of a 2-4 decoder. (b) TFT-level circuit diagram and truth table of an INV. (c) TFT-level circuit diagram and truth table of a NOR. (d) A photograph of a fabricated 2-4 decoder on PI. (e) Measured VTCs of 2-4 decoders fabricated using IGZO:F TFTs. (f) Measured VTCs of 2-4 decoders fabricated using IGZO TFTs. (g) Simulated VTCs of ideal implementation with the same ${V}_{\mathrm{O}\mathrm{N}}$ ~ 0 V for all TFTs. (h) Implementation with ${V}_{\mathrm{O}\mathrm{N}}$ shifts of −4 V for both TFT T8 of the NOR0 gate and the pull-down TFT T6 of the NOR1 gate^[17]. Copyright 2021 IEEE.

DownLoad: Full-Size Img PowerPoint

With ${V}_{\mathrm{D}\mathrm{D}}$ , ${V}_{\mathrm{S}\mathrm{S}}$ and $GND$ set respectively to 5, 12 and 0 V, the voltage-transfer characteristics (VTCs) of decoders implemented using IGZO:F and IGZO TFTs are shown respectively in (e) and (f), where the voltage levels corresponding to the respective logic inputs ${I}_{i}:i=0,\mathrm{ }1$ and logic outputs ${O}_{j}:j=0,\mathrm{ }1,\mathrm{ }2,\mathrm{ }3$ are denoted by ${V}_{{I}_{i}}$ and ${V}_{{O}_{j}}$ . Logic states “0” and “1” correspond respectively to the voltage levels of $GND$ and ${V}_{\mathrm{D}\mathrm{D}}$ . It can be seen from (e) that the decoder built using IGZO:F TFTs operates in a manner close to that of an ideal decoder, i.e, only one output exhibits logic “1”, while the rest exhibits logic “0” for any given input configuration. However, the behavior of the decoder shown in (f) build using IGZO TFTs deviates from that of an ideal decoder: a) When ${V}_{{I}_{1}}$ = 0 V and ${V}_{{I}_{0}}$ = 5 V, ${V}_{{O}_{1}}$ fails to reach 5 V and ${V}_{{O}_{0}}$ fails to reach 0 V. b) When ${V}_{{I}_{1}}$ = 5 V, ${V}_{{O}_{0}}$ is well above 0 V. c) ${V}_{{O}_{3}}$ fail to reach 5 V, when ${V}_{{I}_{0}}$ = ${V}_{{I}_{1}}$ = 5 V.

The simulated VTCs of a 2–4 decoder when ${V}_{{I}_{1}}$ = 0 V are shown in (g) and (h). The measured VTCs of a decoder built using IGZO TFTs are closer to the simulated VTCs when a negative shift of ${V}_{\mathrm{O}\mathrm{N}}$ is imposed. By suppressing the negative shift of ${V}_{\mathrm{O}\mathrm{N}}$ of TFTs, fluorination improves the performance of the decoder. Consequently, the measured VTCs of a decoder built using IGZO:F TFTs is much closer to the simulated VTCs shown in the ideal case when variation is suppressed and all the TFTs in the decoder have the same ${V}_{\mathrm{O}\mathrm{N}}$ .

4. Demonstration flexible electronic systems

4.1 Analog front-end system

Based on the fluorinated SG IGZO TFT technology, an analog front-end (AFE) system for the acquisition of bio-potential signals is designed, fabricated, and characterized^[21]. The architecture of the AFE system is shown in Fig. 5(a), consisting of three sub-systems of (Ⅰ) bias-filters to remove the half cell-potential generated at the contacts between the sensing electrodes and the skin, and to bias the bio-potential to match the operating point of (Ⅱ) a differential amplifier deployed to magnify the bio-potential signal and to suppress the common-mode noise, and (Ⅲ) a notch filter to suppress the power line noise. A fabricated AFE system on the PI placed on the thenar muscle of a hand is shown in (b). IGZO TFTs serve not only as active devices but are also deployed to realize physically small resistors with high resistance. Additionally, the combination of a thermally induced IGZO conductor and the thin gate insulator allows the realization of a physically small capacitor with a large capacitance per unit area. It is the combination of these small components in the bias and notch filters that makes it possible to realize an AFE with a small footprint of ~11 mm². With two of the three electrodes connected to the two inputs ${V}_{\mathrm{I}\mathrm{N}+}$ and ${V}_{\mathrm{I}\mathrm{N}-}$ , and the remaining one to the ground node of the AFE, in-vitro measurements of electromyogram (EMG) and electrocardiogram (ECG) have been performed. The respective electrode connections and the traces of the EMG and ECG are shown in Figs. 5(c) and 5(d).

Fig. 5. (Color online) An AFE system for the acquisition of bio-potential signals. (a) System architecture. (b) PI carrying AFE systems placed on the thenar muscle of a hand. In-vitro measurements of (c) EMG and (d) ECG^[21]. Copyright 2023 Wiley.

DownLoad: Full-Size Img PowerPoint

4.2 Tactile sensor array

Using thin-film piezoelectric polyvinylidene fluoride (PVDF) as a sensing medium, an active-matrix tactile sensor array^[22] has been implemented using the DG ITZO TFT technology. Shown in (a) is the circuit schematic of an in-pixel amplifier consisting of a DG driving TFT M1, a diode-connected SG load TFT M2, and a switching TFT M3. One gate of M1 is employed as an input gate terminal to receive the input signal ${V}_{\mathrm{I}}$ and the other gate is employed as an MG terminal biased at a voltage ${V}_{\mathrm{B}}$ . The corresponding amplified voltage is contained in the output signal ${V}_{\mathrm{O}}$ . The timing diagram associated with the active-matrix addressing of the tactile sensor array is shown in (b). With ${V}_{\mathrm{D}\mathrm{D}}$ = 10 V, ${V}_{\mathrm{L}\mathrm{L}}$ = 4 V and a constant ${V}_{\mathrm{B}}$ = 8 V ((c)), the dependence of the voltage gain ${A}_{\mathrm{V}}$ on ${V}_{\mathrm{I}}$ for 40 in-pixels amplifiers are characterized and shown in (d). Exhibited in (e) are the corresponding ${A}_{\mathrm{V}}$ at ${V}_{\mathrm{I}}$ = 0 V, showing a relatively wide range of 1.5 V/V between −0.5 and −2 V/V.

(Color online) DG ITZO TFT-based in-pixel amplifiers w/ and w/o provision for compensation of TFT parameter variation: (a) circuit schematic and (b) timing diagram; (c) distribution of MG voltage ${V}_{\mathrm{B}}$ for 40 pixel circuits w/ and w/o compensation; (d) dependance of ${A}_{\mathrm{V}}$ on ${V}_{\mathrm{I}}$ and (e) distribution of ${A}_{\mathrm{V}}$ at ${V}_{\mathrm{I}}=0$ V for 40 amplifiers w/o compensation. In-pixel amplifiers w/ provision for compensation of TFT parameter variation: (f) circuit schematic and (g) timing diagram; (h) microscope image of a tactile pixel and (i) photograph of a 16 $\times$ 16 active-matrix tactile sensor array; (j) dependance of ${A}_{\mathrm{V}}$ on ${V}_{\mathrm{I}}$ and (k) distribution of ${A}_{\mathrm{V}}$ at ${V}_{\mathrm{I}}=0$ V for 40 amplifiers w/ compensation^[22]. Copyright 2023 IEEE.

DownLoad: Full-Size Img PowerPoint

The circuit schematic and timing diagrams of an in-pixel amplifier are shown in Figs. 6(f) and 6(g), allowing the application of a compensation scheme. Shown respectively in Figs. 6(h) and (i) are photographs of a 625 × 625 µm tactile pixel and a 16 × 16 tactile sensor array with compensation. With a global compensation signal CMP, the compensation and signal-acquisition scheme operate in two stages: Stage 1 is the compensation phase for setting ${V}_{\mathrm{B}}={V}_{\mathrm{O}}$ and Stage 2 is the acquisition phase for acquiring the signal ${V}_{\mathrm{I}}$ . During Stage 1, the threshold voltage of M1 in every pixel is modulated by switching on M4 and M5 to allow M1 to be consistently biased in the saturation mode. During Stage 2, the compensated ${V}_{\mathrm{B}}$ generated in Stage 1 is stored on the capacitor ${C}_{\mathrm{S}}$ by switching off M4 and M5. The compensated ${V}_{\mathrm{B}}$ shown in (c) ranges between 6.6 and 7.5 V, reflecting the non-uniformity of TFT parameters. The resulting ${A}_{\mathrm{V}}\approx$ −2 V/V varies over a much tighter range of 0.1 V/V, as shown in Figs. 6(j) and 6(k).

A constant ${V}_{\mathrm{B}}$ of 8 V for an uncompensated array and the self-biased ${V}_{\mathrm{B}}$ extracted from a compensated array are shown respectively in (a) and (b). ${V}_{\mathrm{B}}$ in Fig. 7(b) gradually increases from the upper right to the lower left corner of the array, reflecting a systematic trend of the variation of the parameters of the TFTs across the corresponding diagonal of the array. Obtained with the arrays loaded with a letter stamp “O”, respective tactile images w/o and w/ compensation are displayed in Figs. 7(c) and (d). Sharper edges corresponding to better uniformity are observed for the compensated image exhibited in (d). The tactile images acquired using a smaller 8 $\times$ 8 tactile sensor array^[23] are shown in Fig. 7(e), with the mass of the 3D-printed letter and number stamps in the range of dozens of milligrams.

(Color online) MG voltage ${V}_{\mathrm{B}}$ distribution over a 16 $\times$ 16 tactile sensor array (a) w/o and (b) w/ compensation^[22]; tactile images from arrays (c) w/o and (d) w/ compensation when loaded with a letter stamp “O”; (e) tactile images acquired from an 8 × 8 tactile sensor array^[23]. Copyright 2022 and 2023 IEEE.

DownLoad: Full-Size Img PowerPoint

5. Future perspectives

While oxygen deficiency is reported to be responsible for the generation of carrier donors in the S/D regions of a SG TFT processed at 400 °C, a recent kinetic model^[8] suggests the generation of such donors should be negligible at 300 °C. Consequently, the mechanism responsible for the formation of the conductive S/D regions at 300 °C needs to be clarified. Furthermore, the principle behind the O₂-plasma induced activation of the S/D regions in DG TFTs is currently unknown and needs to be investigated.

A schematic system diagram of a more capable bio-potential acquisition system is shown in Fig. 8. In addition to the bias filter, differential amplifier and notch filter are reviewed in the present work, an analog-to-digital converter (ADC) for converting the acquired bio-potential from an analog signal to a digital signal, a wireless module for transmission of the converted signal to a terminal for further data processing and display, and a power management module could also be integrated.

Fig. 8. (Color online) A schematic system diagram of a more capable bio-potential acquisition system on a flexible substrate.

DownLoad: Full-Size Img PowerPoint

A bionic “smart” system consisting of a tactile sensor array and an artificial neural network is shown in Fig. 9. The flexible tactile sensor array based on the integration of PVDF film and DG MO TFTs could be applied to health monitoring, such as pulse-wave measurement. Near-sensor and in-sensor neuromorphic computing were achieved by the artificial neural network which could enable flexible electronic skin with bionic tactile perception.

Fig. 9. (Color online) Flexible tactile sensor array integrated with an artificial neural network as a bionic “smart” system.

DownLoad: Full-Size Img PowerPoint

6. Conclusion

300 °C MO TFT technologies based both on IGZO and ITZO for the implementation of flexible electronic systems have been reviewed. Fluorination has been reported to suppress the variation and shift of ${V}_{\mathrm{O}\mathrm{N}}$ , and DG TFTs have been deployed to modulate the ${V}_{\mathrm{O}\mathrm{N}}$ and to acquire sensor signals. Both are found to improve the robustness and performance of the systems in which they are deployed. Demonstrating the utility of the TFT technologies to the construction of flexible electronic systems, an analog front-end system for the acquisition of bio-potential signals and an active-matrix sensor array for the acquisition of tactile images have been reported.

Acknowledgment

This work was supported by Grant RGC 16215720 from the Science and Technology Program of Shenzhen under JCYJ20200109140601691, Grant GHP/018/21SZ from the Innovation and Technology Fund jointly with Grant SGDX20211123145404006 from the Science and Technology Program of Shenzhen and in part by Fundamental and Applied Fundamental Research Fund of Guangdong Province 2021B1515130001. The devices were fabricated at The Nanosystem Fabrication Facility (NFF) of The Hong Kong University of Science and Technology.

References(23)

References

[1]	Zhu Y, He Y L, Jiang S S, et al. Indium–gallium–zinc–oxide thin-film transistors: Materials, devices, and applications. J Semicond, 2021, 42, 031101 doi: 10.1088/1674-4926/42/3/031101
[2]	Myny K, Lai Y C, Papadopoulos N, et al. A flexible ISO14443-a compliant 7.5mW 128b metal-oxide NFC barcode tag with direct clock division circuit from 13.56MHz carrier. 2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, 258 doi: 10.1109/ISSCC.2017.7870359
[3]	Fuketa H, Yoshioka K, Shinozuka Y, et al. 1µm-thickness 64-channel surface electromyogram measurement sheet with 2V organic transistors for prosthetic hand control. 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 2013, 104 doi: 10.1109/ISSCC.2013.6487656
[4]	Biggs J, Myers J, Kufel J, et al. A natively flexible 32-bit Arm microprocessor. Nature, 2021, 595, 532 doi: 10.1038/s41586-021-03625-w
[5]	Hosono H. How we made the IGZO transistor. Nat Electron, 2018, 1, 428 doi: 10.1038/s41928-018-0106-0
[6]	Xia Z H, Lu L, Li J P, et al. Self-aligned elevated-metal metal-oxide thin-film transistors for displays and flexible electronics. 2019 IEEE International Electron Devices Meeting (IEDM), 2020, 8.4. 1 doi: 10.1109/IEDM19573.2019.8993653
[7]	Wang S S, Shi R X, Li J P, et al. Resilience of fluorinated indium-gallium-zinc oxide thin-film transistor against hydrogen-induced degradation. IEEE Electron Device Lett, 2020, 41, 729 doi: 10.1109/LED.2020.2983789
[8]	Wang Y Q, Jiang W, Xie X Y, et al. A kinetic model for the generation and annihilation of thermally induced carrier donors in a semiconducting metal-oxide thin film. Small, 2022, 18, 2203346 doi: 10.1002/smll.202203346
[9]	Lu L, Xia Z H, Li J P, et al. A comparative study on fluorination and oxidation of indium–gallium–zinc oxide thin-film transistors. IEEE Electron Device Lett, 2018, 39, 196 doi: 10.1109/LED.2017.2781700
[10]	Li J P, Lu L, Feng Z Q, et al. An oxidation-last annealing for enhancing the reliability of indium-gallium-zinc oxide thin-film transistors. Appl Phys Lett, 2017, 110, 142102 doi: 10.1063/1.4979649
[11]	Wang S S, Shi R X, Li J P, et al. 24-2: Distinguished student paper: Fluorination for enhancing the resistance of indium-gallium-zinc oxide thin-film transistor against hydrogen-induced degradation. SID Symp Dig Tech Pap, 2020, 51, 347 doi: 10.1002/sdtp.13875
[12]	Myny K. The development of flexible integrated circuits based on thin-film transistors. Nat Electron, 2018, 1, 30 doi: 10.1038/s41928-017-0008-6
[13]	Spijkman M J, Myny K, Smits E C P, et al. Dual-gate thin-film transistors, integrated circuits and sensors. Adv Mater, 2011, 23, 3231 doi: 10.1002/adma.201101493
[14]	Lei T, Shao L L, Zheng Y Q, et al. Low-voltage high-performance flexible digital and analog circuits based on ultrahigh-purity semiconducting carbon nanotubes. Nat Commun, 2019, 10, 1 doi: 10.1038/s41467-018-07882-8
[15]	Liu F Y, Liu Z H, Gao S Y, et al. Polyimide film with low thermal expansion and high transparency by self-enhancement of polyimide/SiC nanofibers net. RSC Adv, 2018, 8, 19034 doi: 10.1039/C8RA02479K
[16]	Yung K C, Zeng D W, Yue T M. XPS investigation of Upilex-S polyimide ablated by 355 nm Nd: YAG laser irradiation. Appl Surf Sci, 2001, 173, 193 doi: 10.1016/S0169-4332(00)00884-9
[17]	Shi R X, Wang S S, Xia Z H, et al. Fluorinated metal-oxide thin-film transistors for circuit implementation on a flexible substrate. IEEE J Flex Electron, 2022, 1, 58 doi: 10.1109/JFLEX.2021.3140044
[18]	Lu L, Li J P, Kwok H S, et al. High-performance and reliable elevated-metal metal-oxide thin-film transistor for high-resolution displays. 2016 IEEE International Electron Devices Meeting (IEDM), 2017, 32.2. 1 doi: 10.1109/IEDM.2016.7838526
[19]	Xie X, Chen K, Zhou Z, et al. Conductive indium-tin-zinc-oxide formed using an oxygen plasma treatment through a silicon oxide cover layer. in Digest Tech. Papers SID'23 Conference, 2023.
[20]	Huang T C, Fukuda K, Lo C M, et al. Pseudo-CMOS: A design style for low-cost and robust flexible electronics. IEEE Trans Electron Devices, 2011, 58, 141 doi: 10.1109/TED.2010.2088127
[21]	Shi R X, Liu X C, Lei T T, et al. An integrated analog front-end system on flexible substrate for the acquisition of bio-potential signals. Adv Sci, 2023, 10, 2207683 doi: 10.1002/advs.202207683
[22]	Lei T, Hu Y, Xie X, et al. An active-matrix piezoelectric tactile sensor array with in-pixel amplifier and non-uniformity compensation. in Digest Tech. Papers Transducers'23 Conference, 2023.
[23]	Lei T T, Hu Y S, Wong M. Active-matrix tactile sensor array based on the monolithic integration of pvdf and dual-gate transistors. 2022 IEEE 35th International Conference on Micro Electro Mechanical Systems Conference (MEMS), 2022, 71 doi: 10.1109/MEMS51670.2022.9699743