Chin. J. Semicond. > 1997, Volume 18 > Issue 7 > 531-537
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集成电路的连线时延及其在版图设计中的估算

陈春鸿 and 唐璞山

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    Received: 19 August 2015 Revised: Online: Published: 01 July 1997

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      Article Navigation >  Journal of Semiconductors  > 1997  >  18(7): 531-537
      陈春鸿, 唐璞山. 集成电路的连线时延及其在版图设计中的估算[J]. 半导体学报(英文版), 1997, 18(7): 531-537.
      Citation:
      陈春鸿, 唐璞山. 集成电路的连线时延及其在版图设计中的估算[J]. 半导体学报(英文版), 1997, 18(7): 531-537.
      shu

      • Received Date: 2015-08-19

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