| Citation: |
Zhao Gang, Hou Ligang, Luo Rengui, Liu Yuan, Wu Wuchen. Design and Optimization of Low-Power Processor for Wireless Sensor Network[J]. Journal of Semiconductors, 2006, 27(S1): 370-373.
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Zhao G, Hou L G, Luo R G, Liu Y, Wu W C. Design and Optimization of Low-Power Processor for Wireless Sensor Network[J]. Chin. J. Semicond., 2006, 27(13): 370.
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Design and Optimization of Low-Power Processor for Wireless Sensor Network
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Abstract
A low power processor (LPP) for wireless sensor network (WSN) is implemented,based on 90nm technology.In order to reduce power consumption,two methods are selected in the design.Clock gating technique is used to reduce the dynamic power dissipations,and multiple threshold voltage library is adopted to depress leakage power consumption.This paper reports the design results with a brief discussion.-
Keywords:
- low power,
- multi-Vth,
- clock gating,
- wireless sensor network
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References
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Proportional views
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