Abstract: A digital phase-locked loop (DPLL) based on a new digital phase-frequency detector is presented.The self-calibration technique is employed to acquire wide lock range,low jitter,and fast acquisition.The DPLL works from 60 to 600MHz at a supply voltage of 1.8V.It also features a fractional-N synthesizer with digital 2nd-order sigma-delta noise shaping,which can achieve a short lock time,a high frequency resolution,and an improved phase-noise spectrum.The DPLL has been implemented in SMIC 0.18μm 1.8V 1P6M CMOS technology.The peak-to-peak jitter is less than 0.8% of the output clock period and the lock time is less than 150 times of the reference clock period after the pre-divider.

Key words: digital phase-locked loop, phase-frequency detector, self-calibration, voltage controlled oscillator, fractional-N