Chin. J. Semicond. > 2006, Volume 27 > Issue 4 > 730-734
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Breakdown Voltage Analysis of a REBULF LDMOS Structurewith an n+-Floating Layer

Zhang Bo, Duan Baoxing and Li Zhaoji

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Abstract: A novel REBULF (reduced bulk field) concept is proposed for the development of a smart power integrated circuit with a thin epitaxy layer,and a new REBULF LDMOS device structure is designed with an n+-floating layer embedded in the high-resistance substrate.The mechanism of the improved breakdown characteristics is that a high electric field around the drain is reduced by a n+-floating layer,which causes the redistribution of the bulk electric field in the drift region,and the substrate supports more biases.The critical condition of the REBULF,which is analyzed and validated by a 2D MEDICI simulator,is that the product of the location of the n+-floating layer and the substrate doping cannot exceed 1E12cm-2. The breakdown voltage of the REBULF LDMOS is 75% greater than that of a RESURF LDMOS.

Key words: LDMOS,  bulk electric field,  n+-floating layer,  breakdown voltage

1

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Journal of Semiconductors, 2014, 35(8): 084002. doi: 10.1088/1674-4926/35/8/084002
2

An analytical model for the drain-source breakdown voltage of RF LDMOS power transistors with a Faraday shield

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Journal of Semiconductors, 2012, 33(4): 044001. doi: 10.1088/1674-4926/33/4/044001
3

Universal trench design method for a high-voltage SOI trench LDMOS

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Journal of Semiconductors, 2012, 33(7): 074006. doi: 10.1088/1674-4926/33/7/074006
4

ESD robustness studies on the double snapback characteristics of an LDMOS with an embedded SCR

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Journal of Semiconductors, 2011, 32(9): 094002. doi: 10.1088/1674-4926/32/9/094002
5

Super junction LDMOS with enhanced dielectric layer electric field for high breakdown voltage

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Journal of Semiconductors, 2011, 32(2): 024002. doi: 10.1088/1674-4926/32/2/024002
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Breakdown Voltage Characteristics of LDMOS with a Full Depletion Floating Buried Layer

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7

Modeling of High-Voltage LDMOS for PDP Driver ICs

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8

New Lateral Super Junction MOSFETs with n+-Floating Layeron High-Resistance Substrate

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Chinese Journal of Semiconductors , 2007, 28(2): 166-170.

9

A Continuous and Analytical Surface Potential Model for SOI LDMOS

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10

Experiment Results of REBULF LDMOS and Analysis of a Partial n+-Floating Structure

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Chinese Journal of Semiconductors , 2007, 28(8): 1262-1266.

11

A Novel Double RESURF TG-LDMOS Device Structure

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12

Breakdown Characteristic of Multiregion Double RESURF LDMOS with High Voltage Interconnection

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13

Realizing High Breakdown Voltage SJ-LDMOS on Bulk Silicon Using a Partial n-Buried Layer

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14

Research of the Critical Parameters of Power RF LDMOS

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15

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16

Optimization of Breakdown Voltage and On-Resistance Based on the Analysisof the Boundary Curvature of the Drain Region in RF RESURF LDMOS

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17

Development of High Voltage pMOS Devices

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18

A Novel Structure with Multiple Equipotential Rings for Shielding the Influence of a High Voltage Interconnection

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19

On-State Breakdown Model for High Voltage RESURF LDMOS

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20

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    Received: 20 August 2015 Revised: Online: Published: 01 April 2006

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      Article Navigation >  Journal of Semiconductors  > 2006  >  27(4): 730-734
      Zhang Bo, Duan Baoxing, Li Zhaoji. Breakdown Voltage Analysis of a REBULF LDMOS Structurewith an n+-Floating Layer[J]. Journal of Semiconductors, 2006, 27(4): 730-734. ****Zhang B, Duan B X, Li Z J. Breakdown Voltage Analysis of a REBULF LDMOS Structurewith an n+-Floating Layer[J]. Chin. J. Semicond., 2006, 27(4): 730.
      Citation:
      Zhang Bo, Duan Baoxing, Li Zhaoji. Breakdown Voltage Analysis of a REBULF LDMOS Structurewith an n+-Floating Layer[J]. Journal of Semiconductors, 2006, 27(4): 730-734. ****
      Zhang B, Duan B X, Li Z J. Breakdown Voltage Analysis of a REBULF LDMOS Structurewith an n+-Floating Layer[J]. Chin. J. Semicond., 2006, 27(4): 730.
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      Breakdown Voltage Analysis of a REBULF LDMOS Structurewith an n+-Floating Layer

      • IC Design Center,University of Electronic Science & Technology,Chengdu 610054,China

      • IC Design Center,University of Electronic Science & Technology,Chengdu 610054,China

      • IC Design Center,University of Electronic Science & Technology,Chengdu 610054,China

      • Received Date: 2015-08-20

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