Abstract: A 10bit 40MS/s pipelined ADC for DTMB receivers is proposed, which saves power by scaling the capacitor size and the OPA current.The measured results indicate that the ADC exhibits an effective number of bits (ENOB) of 9.14 for 4.9MHz input frequency at 40MS/s, and a spurious free dynamic range (SFDR) of 72.3dB.The measured differential and integral nonlinearities of the prototype at the full sampling rate are less than 0.38 least significant bits (LSB) and 0.51 LSB, respectively.The ADC was fabricated in a 0.18μm 1P6M CMOS process, consumes 78mW of power, and occupies 1mm2.

Key words: analog-to-digital converter, pipeline analog-to-digital converter, spurious free dynamic range