Citation: |
Huang Feipeng, Wang Jingguang, He Jirou, Hong Zhiliang. A 10bit, 50Msample/s,57.6mW CMOS Pipeline A/D Converter[J]. Journal of Semiconductors, 2005, 26(11): 2230-2235.
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Huang F P, Wang J G, He J R, Hong Z L. A 10bit, 50Msample/s,57.6mW CMOS Pipeline A/D Converter[J]. Chin. J. Semicond., 2005, 26(11): 2230.
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A 10bit, 50Msample/s,57.6mW CMOS Pipeline A/D Converter
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Abstract
A 10bit 50MS/s CMOS pipeline A/D converter is implemented in a 1.8V,0.18μm CMOS process.Circuit techniques used to achieve low power consumption include a dynamic comparator,an optimal capacitor, and OTA.Resetting T/H and MADC is adopted to cancel the offset of the OTA.the non-dominant pole of the OTA is optimized to make the OTA work stably.Measured performances include –0.6~0.7LSB of DNL and 44.9dB of SINAD with 5.1MHz input at 50Msample/s.The ADC,with a 57.6mW power consumption and a 0.8mV input offset,occupies a core area of 0.52mm2. -
References
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Proportional views