Delay and Energy Efficient Design of an On-Chip Bus with Repeaters Using a New Spatial and Temporal Encoding Technique

Zhang Qingli; Wang Jinxiang; Yu Mingyan; Ye Yizheng

J. Semicond. > 2008, Volume 29 > Issue 4 > 724-732

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Delay and Energy Efficient Design of an On-Chip Bus with Repeaters Using a New Spatial and Temporal Encoding Technique

Zhang Qingli, Wang Jinxiang, Yu Mingyan and Ye Yizheng

+ Author Affiliations

Abstract: On-chip global buses in deep sub-micron designs consume significant amounts of energy and have large propagation delays.Thus,minimizing energy dissipation and propagation delay is an important design objective.In this paper,we propose a new spatial and temporal encoding approach for generic on-chip global buses with repeaters that enables higher performance while reducing peak energy and average energy.The proposed encoding approach exploits the benefits of a temporal encoding circuit and spatial bus-invert coding techniques to simultaneously eliminate opposite transitions on adjacent wires and reduce the number of self-transitions and coupling-transitions.In the design process of applying encoding techniques for reduced bus delay and energy,we present a repeater insertion design methodology to determine the repeater size and inter-repeater bus length,which minimizes the total bus energy dissipation while satisfying target delay and slew-rate constraints.This methodology is employed to obtain optimal energy versus delay trade-offs under slew-rate constraints for various encoding techniques.

Key words: on-chip buses, delay, energy, encoding, repeaters

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Zhang Qingli, Wang Jinxiang, Yu Mingyan, Ye Yizheng. Delay and Energy Efficient Design of an On-Chip Bus with Repeaters Using a New Spatial and Temporal Encoding Technique[J]. Journal of Semiconductors, 2008, 29(4): 724-732.

Zhang Q L, Wang J X, Yu M Y, Ye Y Z. Delay and Energy Efficient Design of an On-Chip Bus with Repeaters Using a New Spatial and Temporal Encoding Technique[J]. J. Semicond., 2008, 29(4): 724.

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Received: 18 August 2015 Revised: 02 December 2007 Online: Published: 01 April 2008

On-chip global buses in deep sub-micron designs consume significant amounts of energy and have large propagation delays.Thus,minimizing energy dissipation and propagation delay is an important design objective.In this paper,we propose a new spatial and temporal encoding approach for generic on-chip global buses with repeaters that enables higher performance while reducing peak energy and average energy.The proposed encoding approach exploits the benefits of a temporal encoding circuit and spatial bus-invert coding techniques to simultaneously eliminate opposite transitions on adjacent wires and reduce the number of self-transitions and coupling-transitions.In the design process of applying encoding techniques for reduced bus delay and energy,we present a repeater insertion design methodology to determine the repeater size and inter-repeater bus length,which minimizes the total bus energy dissipation while satisfying target delay and slew-rate constraints.This methodology is employed to obtain optimal energy versus delay trade-offs under slew-rate constraints for various encoding techniques.

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