| Citation: |
Mao Xiaojian, Yang Huazhong, Wang Hui. Bias Current Compensation Method with 41.4% Standard Deviation Reduction to MOSFET Transconductance in CMOS Circuits[J]. Journal of Semiconductors, 2006, 27(5): 783-786.
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Mao X J, Yang H Z, Wang H. Bias Current Compensation Method with 41.4% Standard Deviation Reduction to MOSFET Transconductance in CMOS Circuits[J]. Chin. J. Semicond., 2006, 27(5): 783.
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Bias Current Compensation Method with 41.4% Standard Deviation Reduction to MOSFET Transconductance in CMOS Circuits
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Abstract
A simple and successful method for the stability enhancement of integrated circuits is presented.When the process parameters,temperature,and supply voltage are changed,according to the simulation results,this method yields a standard deviation of the transconductance of MOSFETs that is 41.4% less than in the uncompensated case.This method can be used in CMOS LC oscillator design.-
Keywords:
- CMOS,
- transconductance,
- integrated circuits,
- transistor
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References
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Proportional views
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