| Citation: |
Liu Jun, Sun Lingling, Xu Xiaojun. RF-CMOS Modeling:RF-MOSFET Modeling for Low Power Applications[J]. Journal of Semiconductors, 2007, 28(1): 131-137.
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Liu J, Sun L L, Xu X J. RF-CMOS Modeling:RF-MOSFET Modeling for Low Power Applications[J]. Chin. J. Semicond., 2007, 28(1): 131.
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RF-CMOS Modeling:RF-MOSFET Modeling for Low Power Applications
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Abstract
A new RF-MOSFET model for low voltage low power (LVLP) CMOS RFIC CAD application is presented.This model is developed based on the EKVv2.6 model.The gate oxide overlap resistances and the losses of the substrate are cleverly considered.Equivalent circuits biased at zero and linear regions are used to extract all the radio-frequency parasitic parameters analytically.The model is finally used to model an 8-gate-finger (channel mask length L=0.24μm,finger width W=9.58μm) n-MOSFET,which was fabricated in a 0.25μm RF-CMOS process supplied by CSM (Chartered Semiconductor Manufacture Ltd).Comparison of simulated and measured DC data at S-parameters of up to 40GHz demonstrates the excellent accuracy of the model.-
Keywords:
- low voltage low power,
- RF-MOSFET,
- modeling,
- EKVv2.6,
- RF parasitic,
- analytical extraction
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References
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