| Citation: |
Liu Jun, Sun Lingling, Xu Xiaojun. RF-CMOS Modeling:Parasitic Analysis for MOST On-Wafer Test Structure[J]. Journal of Semiconductors, 2007, 28(2): 246-253.
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Liu J, Sun L L, Xu X J. RF-CMOS Modeling:Parasitic Analysis for MOST On-Wafer Test Structure[J]. Chin. J. Semicond., 2007, 28(2): 246.
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RF-CMOS Modeling:Parasitic Analysis for MOST On-Wafer Test Structure
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Abstract
A new model that considers the parasitic effects of a test structure when performing on-wafer S-parameter measurements on RF/microwave MOST fabricated in RF-CMOS technology is presented.Discontinuities between pads and the DUT (device under test) and between stub-interconnect metal and the DUT are considered.The parasitic between the stub-interconnect metal and the lossy substrate is modeled separately.An additional element is introduced to predict the inductive losses of the substrate.All model parameters are directly determined using a simple and analytical measurement-based method,allowing the electrical representation of the complete test structure using an equivalent circuit.The validity of the model is demonstrated by the on-wafer measurements of interconnects up to 40GHz,employing a 0.25μm RF-CMOS process supplied by CSM (Chartered Semiconductor Manufacture Ltd) 0.25μm RF-CMOS technology.-
Keywords:
- RF-CMOS,
- test structure,
- parasitic effect,
- modeling
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References
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