J. Semicond. > 2024, Volume 45 > Issue 8 > 081501
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Review of the SiC LDMOS power device

Ziwei Hu1, 2, 3, §, Jiafei Yao1, 2, 3, §, , Ang Li1, 2, 3, Qi Sun1, 2, 3, Man Li1, 2, Kemeng Yang1, 2, Jun Zhang1, 2, Jing Chen1, 2, Maolin Zhang1, 2 and Yufeng Guo1, 2,

+ Author Affiliations

 Corresponding author: Jiafei Yao, jfyao@njupt.edu.cn; Yufeng Guo, yfguo@njupt.edu.cn

DOI: 10.1088/1674-4926/24010029

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Abstract: Silicon carbide (SiC), as a third-generation semiconductor material, possesses exceptional material properties that significantly enhance the performance of power devices. The SiC lateral double-diffused metal–oxide–semiconductor (LDMOS) power devices have undergone continuous optimization, resulting in an increase in breakdown voltage (BV) and ultra-low specific on-resistance (Ron,sp). This paper has summarized the structural optimizations and experimental progress of SiC LDMOS power devices, including the trench-gate technology, reduced surface field (RESURF) technology, doping technology, junction termination techniques and so on. The paper is aimed at enhancing the understanding of the operational mechanisms and providing guidelines for the further development of SiC LDMOS power devices.

Key words: SiC, LDMOS, specific on-resistance, breakdown voltage



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Fig. 1.  (Color online) Device diagram of the first fabricated 4H-SiC LDMOS power device.

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Fig. 2.  Distributions of Dit at different temperatures. Reproduced with permission from Ref. [17].

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Fig. 3.  (Color online) (a) Cross-sectional view of the lateral RESURF MOSFET. Interface state density for both N2O oxidation and wet O2 oxidation of planar MOSFETs fabricated on the (b) 4H-SiC(0001), (c) 4H-SiC($ 000\bar{\text{1}} $), and (d) 4H-SiC($11 \bar{\text{2}}0 $) faces. Reproduced with permission from Ref. [24].

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Fig. 4.  (Color online) (a) Device diagram of the DGTLDMOS. (b) Device diagram of the SiC LDMOS adopting the double trench gate technology.

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Fig. 5.  (Color online) (a) Device diagram of the DST1-TG LMOS. (b) Device diagram of DST2-TG LMOS. (c) Output J−V characteristics of the studied device with the same epitaxial layer thickness. (d) Ron,sp compositions of the studied devices. Reproduced with permission from Ref. [37].

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Fig. 6.  Schematic equipotential lines and E-field in bulk and at the surface for varying drift region thickness. (a) The drift region thickness is excessive; (b) the RESURF technology has been employed.

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Fig. 7.  (Color online) (a) Device diagram of a 4H-SiC lateral RESURF MOSFET. (b) Device diagram of the designed device incorporating two RESURF zones. (c) Device diagram of a SiC two-zone double RESURF MOSFET.

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Fig. 8.  (Color online) (a) Device diagram of the SiC LMOS with P-top layer and (b) its SEM image. (c) Specific on-resistances and breakdown voltages as a function of the length of Lgap and Lptop by TCAD simulation. (d) Electric field distributions amid points "A" and "B", as well as points "C" and "D" under breakdown condition. Reproduced with permission from Ref. [54].

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Fig. 9.  (Color online) (a) Device diagram, (b) breakdown point A (FN tunneling) and B (avalanche), (c) potential and electric field distribution, and (d) electric field profiles along cutline 1 passing through position A and along cutline 2 through position B of the fabricated 4H-SiC LMOS incorporating a P-top layer by epitaxy technology and Al+ implantation. Reproduced with permission from Ref. [55].

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Fig. 10.  (Color online) (a) Device diagram and (b) the 3D distribution of the surface electric field of the designed device with OPT-VLD P-top layer, and comparison of (c) the turning-on and (d) the turning-off performance of the proposed device and the conventional device. Reproduced with permission from Ref. [58].

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Fig. 11.  (Color online) (a) Device diagram of the SiC LDMOS power device using SD technique. (b) Device diagram of the LDMOS on HPSI substrate incorporating a gate field plate, and its (c) potential distribution and (d) electric field distribution with different length of field gate. Reproduced with permission from Ref. [60].

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Fig. 12.  (Color online) (a) Device diagram of the SiC MR-LDMOS power device. (b) Off-state surface E-field distributions with different Rn. (c) Off-state surface E-field distributions with different Np. Reproduced with permission from Ref. [64].

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Fig. 13.  (Color online) (a) Device diagram of the SiC LDMOS with two BLshape. (b) LW dependences of the breakdown voltage with the drift length of 10 μm. Reproduced with permission from Ref. [67].

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Fig. 14.  (Color online) Schematic view and optimized parameters of the SiC Cir-LDMOS.

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Fig. 15.  (Color online) Trade-off relationship between the BV and Ron,sp of the SiC LDMOS power devices.

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Table 1.   Comparison of properties for SiC and other semiconductors.

Parameters Si GaN 3C-SiC 6H-SiC 4H-SiC
Band gap Eg (eV) 1.1 3.4 2.3 3.03 3.25
Electron mobility μ (cm2/(V·s)) 1400 900 1000 450 1000
Relative dielectric constant ε 11.8 9.0 9.7 9.7 9.7
Thermal conductivity λ (W/(cm·k)) 1.5 2.0 4.9 4.9 4.9
Breakdown electric field Eb (MV/cm) 0.3 3.3 4 5 2.5
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Table 2.   Comparison of electric performances for SiC LDMOS power devices.

Structures Channel mobility
(cm2/(V∙s))		 Ron,sp
(mΩ∙cm2)		 BV
(V)		 BFOM (MW/cm2) Current Refs Experiment (E)
or simulation (S)
The first 4H-SiC LDMOS 5 200 2600 33 0.25 mA
(Vgs = 25 V)		 [9] E
4H-SiC lateral MOSFET with
NO annealing		 25 170 930 5.09 6.5 mA
(Vgs = 24 V)		 [20] E
6H-SiC lateral MOSFET with
two RESURF zones		 30 160 1300 10.56 25 mA
(Vgs = 30 V)		 [48] E
4H-SiC lateral MOSFET with two-zone RESURF 17 66 1380 28.85 20 mA [52] E
4H-SiC LDMOS on HPSI substrate 35 600 3520 20.6 / [61] E
4H-SiC LDMOS with trench-gate structure / 97 440 1.99 1.2 mA/μm
(Vgs = 10 V)		 [35] S
4H-SiC LDMOS with gate field plates / 59.75 934 14.6 19 mA/mm
(Vgs = 25 V)		 [60] E
4H-SiC LDMOS with current path layer 21.7 89.8 1093 13.3 22 mA/mm
(Vgs = 25 V)		 [71] E
SiC LDMOS with two L-shaped oxide layers / 18.79 1220 79.2 / [67] S
4H-SiC lateral MOSFET with a
P-top layer		 17 13.7 600 97.3 10 A
(Vgs = 25 V)		 [54] E
4H-SiC LDMOS with double-trench gate / 3.5 1460 609 1 mA
(Vgs = 20 V)		 [36] S
4H-SiC lateral MOSFET with dual source trenches 50 3.9 1540 608.1 / [37] S
SiC lateral MOSFET with VLD
P-top layer		 31 3.57 1500 630.2 0.8 A/mm
(Vgs = 20 V)		 [58] S
SiC lateral MOSFETS with SD
P-top layer		 / 4.04 1934 925.8 / [59] S
DownLoad: CSV
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[2]
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[4]
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    Received: 30 January 2024 Revised: 29 March 2024 Online: Accepted Manuscript: 29 April 2024Uncorrected proof: 06 May 2024Published: 15 August 2024

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      Article Navigation >  Journal of Semiconductors  > 2024  >  45(8): 081501
      Ziwei Hu, Jiafei Yao, Ang Li, Qi Sun, Man Li, Kemeng Yang, Jun Zhang, Jing Chen, Maolin Zhang, Yufeng Guo. Review of the SiC LDMOS power device[J]. Journal of Semiconductors, 2024, 45(8): 081501. doi: 10.1088/1674-4926/24010029 ****Z W Hu, J F Yao, A Li, Q Sun, M Li, K M Yang, J Zhang, J Chen, M L Zhang, and Y F Guo, Review of the SiC LDMOS power device[J]. J. Semicond., 2024, 45(8), 081501 doi: 10.1088/1674-4926/24010029
      Citation:
      Ziwei Hu, Jiafei Yao, Ang Li, Qi Sun, Man Li, Kemeng Yang, Jun Zhang, Jing Chen, Maolin Zhang, Yufeng Guo. Review of the SiC LDMOS power device[J]. Journal of Semiconductors, 2024, 45(8): 081501. doi: 10.1088/1674-4926/24010029 ****
      Z W Hu, J F Yao, A Li, Q Sun, M Li, K M Yang, J Zhang, J Chen, M L Zhang, and Y F Guo, Review of the SiC LDMOS power device[J]. J. Semicond., 2024, 45(8), 081501 doi: 10.1088/1674-4926/24010029
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      Review of the SiC LDMOS power device

      DOI: 10.1088/1674-4926/24010029
      • 1.

        College of Integrated Circuit Science and Engineering (Industry-Education Integration School), Nanjing University of Posts and Telecommunications, Nanjing 210023, China

      • 2.

        National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology, Nanjing 210023, China

      • 3.

        Nantong Institute of Nanjing University of Posts and Telecommunications, Nantong 226000, China

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      • Ziwei Hu received his bachelor's degree from Nanjing University of Posts and Telecommunications in 2023. Now he is a Ph. D. candidate student at Nanjing University of Posts and Telecommunications under the supervision of Prof. Yufeng Guo. He focuses on the research of silicon carbide power devices
      • Jiafei Yao received his Ph.D. degree in microelectronics and solid-state electronics from Nanjing University of Posts and Telecommunications. Currently, he is an associate professor with the School of Integrated Circuit Science and Engineering, Nanjing University of Posts and Telecommunications, Nanjing, China. His research focuses on the silicon power devices, silicon carbide power devices and power integrated circuits
      • Yufeng Guo received the Ph.D. degree in microelectronics and solid-state electronics from the University of Electronic Science and Technology of China, Chengdu, China, in 2005. He is currently a Professor with the School of Integrated Circuit Science and Engineering, Nanjing University of Posts and Telecommunications, Nanjing, China. He has published more than 250 articles in refereed journals and conferences and holding over 60 Chinese patents. His current research interests include semiconductor power devices, microelectronics devices reliability, and RF and power integrated circuits and systems
      • Corresponding author: jfyao@njupt.edu.cn; yfguo@njupt.edu.cn
      • Received Date: 2024-01-30
      • Revised Date: 2024-03-29
        • Available Online: 2024-04-29

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