Fig. 1.
(Color online) The current mode BGR core.
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Journal of Semiconductors
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2025
> Accepted Manuscript
| Citation: |
Jing Wang, Feixiang Zhang, Zhiyuan He, Hui Zhang, Lin Cheng. A 2.69 ppm/°C bandgap reference with 42 ppm/V line sensitivity for battery management system[J]. Journal of Semiconductors, 2025, In Press. doi: 10.1088/1674-4926/24120045
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J Wang, F X Zhang, Z Y He, H Zhang, and L Cheng, A 2.69 ppm/°C bandgap reference with 42 ppm/V line sensitivity for battery management system[J]. J. Semicond., 2025, accepted doi: 10.1088/1674-4926/24120045
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A 2.69 ppm/°C bandgap reference with 42 ppm/V line sensitivity for battery management system
DOI: 10.1088/1674-4926/24120045
CSTR: 32376.14.1674-4926.24120045
More Information-
Jing Wang received the B.Eng. degree from Sichuan University, Chengdu, China, in 2011. Then, she received the M. Sc. degree in 2012 and the Ph.D. degree in 2017 from Waseda University, Fukuoka, Japan, respectively. From 2017 to 2019, she was a post doctor in Waseda University, Japan. She is currently an associate researcher at the University of Science and Technology of China. Her research focuses on the design of high-precision, low-power analog front-end (AFE) circuits -
Lin Cheng received the B.Eng. degree from Hefei University of Technology, Hefei, China, in 2008, the M. Sc. degree from Fudan University, Shanghai, China, in 2011, and the Ph.D. degree from Hong Kong University of Science and Technology (HKUST), Hong Kong, in 2016. In 2018, he joined the School of Microelectronics, University of Science and Technology of China, Hefei, where he is currently a Professor. He was a Post-doctoral Research Associate at the Department of Electronic and Computer Engineering, HKUST, from 2016 to 2018, and was an Intern Analog Design Engineer with Broadcom Limited, San Jose, CA, USA, from 2015 to 2016. His current research interests include power management and mixed-signal integrated circuits and systems, wireless power transfer circuits and systems, switched-inductor power converters, and automotive ICs. Dr. Cheng is serving as a member of the ISSCC Technical Committee and the Chair of the IEEE ICTA 2024 Technical Committee. He was a recipient of the IEEE Solid-State Circuits Society Pre-Doctoral Achievement Award from 2014 to 2015, the Hong Kong Institution of Science 2018 Young Scientist Awards (Honorable Mention), and the Best Design Award from the IEEE ASP-DAC University Design Contest in 2020 - Corresponding author: eecheng@ustc.edu.cn
- Revised Date: 2025-03-25 Available Online: 2025-04-30
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Abstract
This paper introduces a high-precision bandgap reference (BGR) designed for battery management systems (BMS), featuring an ultra-low temperature coefficient (TC) and line sensitivity (LS). The BGR employs a current-mode scheme with chopped op-amps and internal clock generators to eliminate op-amp offset. A low dropout regulator (LDO) and a pre-regulator enhance output driving and LS, respectively. Curvature compensation enhances the TC by addressing higher-order nonlinearity. These approaches, effective near room temperature, employs trimming at both 20 and 60 °C. When combined with fixed curvature correction currents, it achieves an ultra-low TC for each chip. Implemented in a CMOS 180 nm process, the BGR occupies 0.548 mm² and operates at 2.5 V with 84 μA current draw from a 5 V supply. An average TC of 2.69 ppm/°C with two-point trimming and 0.81 ppm/°C with multi-point trimming are achieved over the temperature range of −40 to 125 °C. It accommodates a load current of 1 mA and an LS of 42 ppm/V, making it suitable for precise BMS applications. -
References
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