Yield-aware optimization of memory gate length in split-gate SONOS: trade-off between erase efficiency and lithography process window

Zhexuan Li; Xiao Yu; Liyang Pan; Dawei Gao; Dianyu Qi; Kun Ren

doi:10.1088/1674-4926/26020016

J. Semicond. > Just Accepted

ARTICLES

Yield-aware optimization of memory gate length in split-gate SONOS: trade-off between erase efficiency and lithography process window

Zhexuan Li¹, Xiao Yu², Liyang Pan³, Dawei Gao^{1, 4}, Dianyu Qi^{1, 4} and Kun Ren^{1, 4,}

+ Author Affiliations

Corresponding author: Kun Ren, kun.ren@zju.edu.cn

DOI: 10.1088/1674-4926/26020016CSTR: 32376.14.1674-4926.26020016

Abstract: A yield-aware optimization strategy is proposed to address the Trapped Charge Mismatch Effect (TCME) in split-gate SONOS flash by bridging device physics with lithography constraints. The study demonstrates that scaling the memory gate length (L_MD) induces a lateral field extension that physically minimizes the region of residual trapped electrons. However, a fundamental physics-lithography trade-off is identified: while aggressive scaling maximizes erase efficiency, Process Variation Band (PVB) analysis mandates a 50 nm manufacturable optimum to maintain Critical Dimension (CD) variation within the 10% safety threshold. Experimental verification on an 8 Mb array confirms the strategy's effectiveness, achieving 99.3% yield and suppressing bit-to-bit disturbance to 10.9% of the memory window (MW). Supported by endurance exceeding 10⁵ cycles, these results demonstrate a viable high-yield pathway for scaling high-reliability memories.

Keywords: yield optimization, lithography process window, SONOS, split-gate, TCAD

References

[1]	Jangra P, Duhan M. Performance-based comparative study of existing and emerging non-volatile memories: A review. J Opt, 2023, 52(4): 2395 doi: 10.1007/s12596-022-01058-w
[2]	Elsherbini A, Jun K, Liff S, et al. Enabling next generation 3D heterogeneous integration architectures on intel process. 2022 International Electron Devices Meeting (IEDM). San Francisco, CA, USA. IEEE, 2023: 27.3. 1
[3]	Choi H, Yoo J, Shin H. A new physical model for program transients of cylindrical charge-trap-based NAND flash memories. IEEE Trans Electron Devices, 2024, 71(4): 2386 doi: 10.1109/TED.2024.3364587
[4]	Taniguchi Y, Yoshida S, Egashira T, et al. SONOS embedded flash IP using trap-depth-controlled SiN film enabling data retention more than 10 years at 200°C. 2023 IEEE International Memory Workshop (IMW). Monterey, CA, USA. IEEE, 2023: 1
[5]	Hur J, Kang D, Moon D I, et al. Cryogenic storage memory with high-speed, low-power, and long-retention performance. Adv Electron Mater, 2023, 9(6): 2201299 doi: 10.1002/aelm.202201299
[6]	Li Z X, Yu X, Ren K, et al. A novel dual-bit charge trapping flash cell with operation optimization for standalone and embedded universal applications. 2024 IEEE International Electron Devices Meeting (IEDM), 2025: 1
[7]	Jiang C M, Wu C J, Wang T H. Numerical simulation of trapped hole lateral migration and induced threshold voltage retention loss in a SONOS flash memory. IEEE Trans Device Mater Reliab, 2023, 23(1): 147 doi: 10.1109/TDMR.2023.3240777
[8]	Wei Y D, Liu G Z, Wei J H, et al. Degradation behavior and mechanism of SONOS FLASH by total ionization dose effects. IEEE Trans Device Mater Reliab, 2025, 25(1): 128 doi: 10.1109/TDMR.2024.3524100
[9]	Park S K, Kim S D, Lee B H. Development of 2T-SONOS cell using a contamination-free process integration for a highly reliable code storage eNVM. IEEE Trans Electron Devices, 2020, 67(3): 922 doi: 10.1109/TED.2020.2966501
[10]	Son D, Park J, Shin H. Investigation and compact modeling of hot-carrier injection for read disturbance in 3-D NAND flash memory. IEEE Trans Electron Devices, 2020, 67(7): 2778 doi: 10.1109/TED.2020.2993772
[11]	Sung C L, Lue H-T, Chen W-C, et al. First study of P-channel vertical split-gate flash memory device with various electron and hole injection methods and potential future possibility to enable functional memory circuits. 2021 IEEE International Memory Workshop (IMW), 2021: 1
[12]	Wang K X, Lu J, Xiang Z Y, et al. Engineering improvement of the core layers of charge trapping flash memory based on doped HfO₂ and segmented fabrication. Electronics, 2024, 13(9): 1642 doi: 10.3390/electronics13091642
[13]	Kim Y, Kim S. A process-aware compact model for GIDL-assisted erase optimization of 3-D V-NAND flash memory. IEEE Trans Electron Devices, 2023, 70(4): 1664 doi: 10.1109/TED.2023.3246024
[14]	Ling W Y, Ren K, Qi D Y, et al. Investigation of L-shaped split-gate eFlash memory with enhanced gate coupling in a 55 nm node. Appl Phys Lett, 2025, 127(8): 082102 doi: 10.1063/5.0266252
[15]	Jourba S, Bollon N, Decobert C, et al. Performance and reliability of 4 mb eFLASH memory array featuring 28 nm split-gate cell with HKMG select transistor. 2020 IEEE International Memory Workshop (IMW), 2020: 1
[16]	Ahn S, Jo H, Park S, et al. Investigation of cell variation effect on Z-interference in charge-trap-based 3-D NAND flash memory. IEEE Trans Electron Devices, 2025, 72(3): 1141 doi: 10.1109/TED.2025.3534187
[17]	Yoo J, Kim S, Jeon W, et al. A study on the charge trapping characteristics of high-k laminated traps. IEEE Electron Device Lett, 2019, 40(9): 1427 doi: 10.1109/LED.2019.2932007
[18]	Sturtevant J L, Yin L H, Kim Y C, et al. Process window-based feature and die failure rate prediction. Design-Process-Technology Co-optimization for Manufacturability XIII, 2019: 10
[19]	Sze S M, Li Y, Ng K K. Physics of semiconductor devices. Hoboken: John Wiley & Sons, 2021
[20]	Hu C M, Tam S C, Hsu F C, et al. Hot-electron-induced MOSFET degradation: Model, monitor, and improvement. IEEE Trans Electron Devices, 1985, 32(2): 375 doi: 10.1109/T-ED.1985.21952
[21]	Yin X Z, Barkam H E, Müller F, et al. A remedy to compute-in-memory with dynamic random access memory: 1FeFET-1C technology for neuro-symbolic AI. 2024: arXiv: 2410.15296. https://arxiv.org/abs/2410.15296
[22]	Lue H T, Hsu T H, Wu M T, et al. Studies of the reverse read method and second-bit effect of 2-bit/cell nitride-trapping device by quasi-two-dimensional model. IEEE Trans Electron Devices, 2006, 53(1): 119 doi: 10.1109/TED.2005.860644

Fig. 1. (Color online) Schematic cross-section of the dual-bit split-gate SONOS memory cell architecture.

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Fig. 2. (Color online) TCAD-simulated 2D electrostatic potential distribution of the split-gate SONOS cell under BBHH erase bias condition.

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Fig. 3. (Color online) Comparison of electric field distributions along the channel under BBHH erase bias condition for different L_MD values. (a)-(b) Lateral and vertical electric fields before the erase operation. (c)-(d) Lateral and vertical electric fields after the erase operation.

DownLoad: Full-Size Img PowerPoint

Fig. 4. (Color online) TCAD-simulated 2D spatial distributions of trapped charges in the silicon nitride layer across varying L_MD (40–60 nm). The profiles depict the device state after a full P/E cycle comprising 10 μs CHE programming and 10 ms BBHH erasing. The top row (a)-(e) displays the injected hole coverage, while the bottom row (f)-(j) visualizes the residual electron distribution, with percentages quantifying the un-neutralized charge ratio.

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Fig. 5. (Color online) TCAD-simulated evolution of the integrated (a) trapped electron charge and (b) trapped hole charge in the silicon nitride layer during a 100-ms BBHH erase operation.

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Fig. 6. (Color online) Simulated I_D-V_G characteristics for dual-bit SONOS devices with different L_MD after a P/E cycle (10 μs CHE programming and 10 ms BBHH erasing).

DownLoad: Full-Size Img PowerPoint

Fig. 7. (Color online) (a) Schematic illustration of the PVB concept in lithography simulation. (b) Statistical analysis of the PVB width and the relative CD variation (±ΔCD/CD) as a function of the ADI CD.

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Fig. 8. (Color online) FEM measurements for the optimized L_MD = 50 nm. The green region defines the safe process window, while red regions indicate failure modes.

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Fig. 9. Cross-sectional TEM images of the fabricated dual-bit SONOS device. (a) Overview of the memory array structure. (b) Magnified view of a single memory cell. (c) Cross-sectional view of the O-N-O gate stack.

DownLoad: Full-Size Img PowerPoint

Fig. 10. (Color online) Wafer-level statistical characterization of the 8 Mb test array fabricated with the optimized L_MD = 50 nm design. (a) Yield distribution map across a representative wafer. (b) Statistical distribution of the V_TH for MG; (c)-(d) Statistical distributions of V_TH for MS and MD, respectively.

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Fig. 11. (Color online) Measured electrical characteristics of the fabricated 50 nm array. (a) Superimposed I_D-V_G transfer curves of 10 randomly selected cells after P/E cycling. (b) Characterization of bit-to-bit disturbance.

DownLoad: Full-Size Img PowerPoint

Fig. 12. (Color online) Endurance and retention characteristics of the optimized 50 nm dual-bit SONOS cell. (a) Cumulative I_D-V_G characteristics at different P/E cycle counts during endurance testing. (b) Extracted V_TH evolution during P/E cycling. (c) Cumulative I_D-V_G characteristics at different baking time intervals during 175 °C retention testing. (d) Extracted V_TH evolution during 175 °C baking.

DownLoad: Full-Size Img PowerPoint

Table 1. Operation conditions for MD.

Operate	Scheme	Typical conditions (e.g., MD)
Program	CHE	V_D = 4.4 V, V_S = 0.2 V, V_MS = 5 V, V_MG = 1 V, V_MD = 6.4 V; T_W = 10 μs;
Erase	BBHH	V_D = 5.4 V, V_S = 1.8 V, V_MS = 0 V, V_MG = 0 V, V_MD = –5.4 V; T_E = 10 ms;
Read	Reverse	V_D = 0 V, V_S = 1 V, V_MS = 5 V, V_MG = 2.5 V, V_MD = V_RG = 1 V;

DownLoad: CSV

[1]	Jangra P, Duhan M. Performance-based comparative study of existing and emerging non-volatile memories: A review. J Opt, 2023, 52(4): 2395 doi: 10.1007/s12596-022-01058-w
[2]	Elsherbini A, Jun K, Liff S, et al. Enabling next generation 3D heterogeneous integration architectures on intel process. 2022 International Electron Devices Meeting (IEDM). San Francisco, CA, USA. IEEE, 2023: 27.3. 1
[3]	Choi H, Yoo J, Shin H. A new physical model for program transients of cylindrical charge-trap-based NAND flash memories. IEEE Trans Electron Devices, 2024, 71(4): 2386 doi: 10.1109/TED.2024.3364587
[4]	Taniguchi Y, Yoshida S, Egashira T, et al. SONOS embedded flash IP using trap-depth-controlled SiN film enabling data retention more than 10 years at 200°C. 2023 IEEE International Memory Workshop (IMW). Monterey, CA, USA. IEEE, 2023: 1
[5]	Hur J, Kang D, Moon D I, et al. Cryogenic storage memory with high-speed, low-power, and long-retention performance. Adv Electron Mater, 2023, 9(6): 2201299 doi: 10.1002/aelm.202201299
[6]	Li Z X, Yu X, Ren K, et al. A novel dual-bit charge trapping flash cell with operation optimization for standalone and embedded universal applications. 2024 IEEE International Electron Devices Meeting (IEDM), 2025: 1
[7]	Jiang C M, Wu C J, Wang T H. Numerical simulation of trapped hole lateral migration and induced threshold voltage retention loss in a SONOS flash memory. IEEE Trans Device Mater Reliab, 2023, 23(1): 147 doi: 10.1109/TDMR.2023.3240777
[8]	Wei Y D, Liu G Z, Wei J H, et al. Degradation behavior and mechanism of SONOS FLASH by total ionization dose effects. IEEE Trans Device Mater Reliab, 2025, 25(1): 128 doi: 10.1109/TDMR.2024.3524100
[9]	Park S K, Kim S D, Lee B H. Development of 2T-SONOS cell using a contamination-free process integration for a highly reliable code storage eNVM. IEEE Trans Electron Devices, 2020, 67(3): 922 doi: 10.1109/TED.2020.2966501
[10]	Son D, Park J, Shin H. Investigation and compact modeling of hot-carrier injection for read disturbance in 3-D NAND flash memory. IEEE Trans Electron Devices, 2020, 67(7): 2778 doi: 10.1109/TED.2020.2993772
[11]	Sung C L, Lue H-T, Chen W-C, et al. First study of P-channel vertical split-gate flash memory device with various electron and hole injection methods and potential future possibility to enable functional memory circuits. 2021 IEEE International Memory Workshop (IMW), 2021: 1
[12]	Wang K X, Lu J, Xiang Z Y, et al. Engineering improvement of the core layers of charge trapping flash memory based on doped HfO₂ and segmented fabrication. Electronics, 2024, 13(9): 1642 doi: 10.3390/electronics13091642
[13]	Kim Y, Kim S. A process-aware compact model for GIDL-assisted erase optimization of 3-D V-NAND flash memory. IEEE Trans Electron Devices, 2023, 70(4): 1664 doi: 10.1109/TED.2023.3246024
[14]	Ling W Y, Ren K, Qi D Y, et al. Investigation of L-shaped split-gate eFlash memory with enhanced gate coupling in a 55 nm node. Appl Phys Lett, 2025, 127(8): 082102 doi: 10.1063/5.0266252
[15]	Jourba S, Bollon N, Decobert C, et al. Performance and reliability of 4 mb eFLASH memory array featuring 28 nm split-gate cell with HKMG select transistor. 2020 IEEE International Memory Workshop (IMW), 2020: 1
[16]	Ahn S, Jo H, Park S, et al. Investigation of cell variation effect on Z-interference in charge-trap-based 3-D NAND flash memory. IEEE Trans Electron Devices, 2025, 72(3): 1141 doi: 10.1109/TED.2025.3534187
[17]	Yoo J, Kim S, Jeon W, et al. A study on the charge trapping characteristics of high-k laminated traps. IEEE Electron Device Lett, 2019, 40(9): 1427 doi: 10.1109/LED.2019.2932007
[18]	Sturtevant J L, Yin L H, Kim Y C, et al. Process window-based feature and die failure rate prediction. Design-Process-Technology Co-optimization for Manufacturability XIII, 2019: 10
[19]	Sze S M, Li Y, Ng K K. Physics of semiconductor devices. Hoboken: John Wiley & Sons, 2021
[20]	Hu C M, Tam S C, Hsu F C, et al. Hot-electron-induced MOSFET degradation: Model, monitor, and improvement. IEEE Trans Electron Devices, 1985, 32(2): 375 doi: 10.1109/T-ED.1985.21952
[21]	Yin X Z, Barkam H E, Müller F, et al. A remedy to compute-in-memory with dynamic random access memory: 1FeFET-1C technology for neuro-symbolic AI. 2024: arXiv: 2410.15296. https://arxiv.org/abs/2410.15296
[22]	Lue H T, Hsu T H, Wu M T, et al. Studies of the reverse read method and second-bit effect of 2-bit/cell nitride-trapping device by quasi-two-dimensional model. IEEE Trans Electron Devices, 2006, 53(1): 119 doi: 10.1109/TED.2005.860644

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Received: 26 February 2026 Revised: 21 April 2026 Online: Accepted Manuscript: 28 July 2026

Article Navigation > Journal of Semiconductors > 2026 > Accepted Manuscript

Zhexuan Li, Xiao Yu, Liyang Pan, Dawei Gao, Dianyu Qi, Kun Ren. Yield-aware optimization of memory gate length in split-gate SONOS: trade-off between erase efficiency and lithography process window[J]. Journal of Semiconductors, 2026, In Press. doi: 10.1088/1674-4926/26020016 ****Z X Li, X Yu, L Y Pan, D W Gao, D Y Qi, and K Ren, Yield-aware optimization of memory gate length in split-gate SONOS: trade-off between erase efficiency and lithography process window[J]. J. Semicond., 2026, accepted doi: 10.1088/1674-4926/26020016

Citation:

Z X Li, X Yu, L Y Pan, D W Gao, D Y Qi, and K Ren, Yield-aware optimization of memory gate length in split-gate SONOS: trade-off between erase efficiency and lithography process window[J]. J. Semicond., 2026, accepted doi: 10.1088/1674-4926/26020016

Citation:

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Yield-aware optimization of memory gate length in split-gate SONOS: trade-off between erase efficiency and lithography process window

DOI: 10.1088/1674-4926/26020016

CSTR: 32376.14.1674-4926.26020016

Zhexuan Li¹,
Xiao Yu²,
Liyang Pan³,
Dawei Gao^{1, 4},
Dianyu Qi^{1, 4},
Kun Ren^{1, 4,}

1.
College of Integrated Circuits, Zhejiang University, Hangzhou 310000, China
2.
Hangzhou Institute of Technology, Xidian University, Hangzhou 311200, China
3.
School of Integrated Circuits, Tsinghua University, Beijing 100084, China
4.
Zhejiang ICsprout Semiconductor, Hangzhou 311200, China

More Information

Zhexuan Li got his B.S. degree from Beijing University of Chemical Technology in 2019 and the M.S. degree from Sun Yat-sen University in 2022. He is currently pursuing the Ph.D. degree with Zhejiang University. His main research interests include fabrication and optimization of charge-trapping memory devices
Kun Ren is currently a research fellow at Zhejiang University. His primary research interests include industrial-oriented computational lithography EDA technology, embedded memory technology, as well as design and technology co-optimization
Corresponding author: kun.ren@zju.edu.cn
Received Date: 2026-02-26
Revised Date: 2026-04-21

Available Online: 2026-07-28

Abstract

Abstract

A yield-aware optimization strategy is proposed to address the Trapped Charge Mismatch Effect (TCME) in split-gate SONOS flash by bridging device physics with lithography constraints. The study demonstrates that scaling the memory gate length (L_MD) induces a lateral field extension that physically minimizes the region of residual trapped electrons. However, a fundamental physics-lithography trade-off is identified: while aggressive scaling maximizes erase efficiency, Process Variation Band (PVB) analysis mandates a 50 nm manufacturable optimum to maintain Critical Dimension (CD) variation within the 10% safety threshold. Experimental verification on an 8 Mb array confirms the strategy's effectiveness, achieving 99.3% yield and suppressing bit-to-bit disturbance to 10.9% of the memory window (MW). Supported by endurance exceeding 10⁵ cycles, these results demonstrate a viable high-yield pathway for scaling high-reliability memories.
- yield optimization,
- lithography process window,
- SONOS,
- split-gate,
- TCAD

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