Ye Lin received the B.S. degree in electronic information science and technology from Ningbo University, Ningbo, China, in 2023. He is currently pursuing the M.S. degree with the School of Electronic Science and Engineering, Nanjing University, Nanjing, China. His research interests include analog and mixed-signal circuits for deep learning accelerators.
Boheng Jiang received the B.S. degree from the School of Electronic Science and Engineering, Nanjing University, Nanjing, China, in 2025. He is currently pursuing the M.S. degree with the School of Electronic Science and Engineering, Nanjing University, Nanjing, China. His research interests include charge trap transistors (CTTs) and floating-point computing-in-memory (FP-CIM).
Jiayuan Chen received her Bachelor’s degree from the Department of Information Engineering, Nanjing University of Posts and Telecommunications in 2003, and her Ph.D. degree from the Department of Electronic and Electrical Engineering from University College London (UCL), United Kingdom, in 2008. From September 2009 to January 2011, she joined the Innovation Lab of Alcatel-Lucent Shanghai Bell as a Research Scientist. Since March 2011, she has been with the Network and IT Technology Research Institute, China Mobile Research Institution, where her research focuses on GPU scale-up interconnection, AI infrastructure and NFV/SDN network transformation.
Dawei Li (Member, IEEE) received the B.S. degree in elec-trical engineering from the Wuhan University of Science and Technology, Wuhan, China, in 2010, and the Ph.D. degree in electrical engineering from the Huazhong University of Science and Technology, Wuhan, in 2017. He is currently an Associate Professor with South-Central Minzu University, Wuhan. His current research interests in-clude wireline & wireless & power management.
Yuan Du (S’14-M’17-SM’21) received his B.S. degree from Southeast University (SEU), Nanjing, China, in 2009, his M.S. and his Ph.D. degree both from Electrical Engineering Department, University of California, Los Angeles (UCLA), in 2012 and 2016, respectively. Since 2019, he has been with Nanjing University, Nanjing, China, as an Associate Professor. He worked for Kneron Inc., San Diego, CA, USA from 2016 to 2019, as a leading hardware architect. His current research interests include designs of machine-learning hardware accelerators, high-speed inter-chip/intra-chip interconnects, and RFICs. He was the recipient of the Microsoft Research Asia Young Fellow (2008), Southeast University Chancellor’s Award (2009), Broadcom Young Fellow (2015), and IEEE Circuits and Systems Society Darlington Best Paper Award (2021).
Li Du (M’16) received his B.S degree from Southeast University, Nanjing, China, in 2011, and his Ph.D. degree in Electrical Engineering from the University of California, Los Angeles, CA, USA, in 2016. From June 2013 to Sept 2016, he worked at Qualcomm Inc., San Diego, CA, USA, designing mixed-signal circuits for cellular communications. From Sept. 2016 to Oct. 2018, he worked at Kneron Inc., San Diego, CA, USA, as a hardware architect research scientist, designing high-performance artificial intelligence (AI) hardware accelerators. After that, he joined Xin Yun Tech Inc., Westlake, CA, USA, in charge of high-speed analog circuits design for 100G/400G optical communication. Currently, he is a professor in the department of School of Integrated Circuits at Nanjing University. His research includes analog sensing circuit design, in-memory computing design, and a high-performance AI processor for edge sensing.
Fig. 1.
(Color online) (a) Schematic of the high-precision matrix inversion (HP-INV), composed of iterative LP-INV and HP-MVM operations. (b) Schematic of the memory cell, switch, and slave transistor, where locally stored weight data controls the effective geometric ratio of the computing stage, rather than relying on the intrinsic physical properties of the memory device. (c) Calibration of scaling and bias drift by adjusting the reference voltages of the SAR ADC. (d) Error-correction quantization (ECQ) framework. (e) Schematic of the overall reconfigurable analog circuitry employing Taylor approximations to fit arbitrary nonlinear functions. (f) Ramp nonlinear ADCs that embed nonlinear transfer functions directly into the conversion process of single-slope ADCs. (g) Analog circuit implementation of the overall special function (SF) unit.
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