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Advanced baseband chip designs for B5G and 6G

Chuan Zhang, Yiwei Zhang, Yu Tian, Kangqi Wu, Kunying Li, Houren Ji, Wenyue Zhou, Yi Zhang and Xiaohu You

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 Corresponding author: Chuan Zhang, chzhang@seu.edu.cn; Xiaohu You, xhyu@seu.edu.cn

DOI: 10.1088/1674-4926/26020043CSTR: 32376.14.1674-4926.26020043

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[1]
Studer C, Fateh S, Seethaler D. ASIC implementation of soft-input soft-output MIMO detection using MMSE parallel interference cancellation. IEEE J Solid State Circuits, 2011, 46(7): 1754 doi: 10.1109/JSSC.2011.2144470
[2]
Zhou W Y, Ji Z H, Tan Z Q, et al. Approximate belief-selective propagation detector for massive MIMO systems. IEEE Trans Circuits Syst I Regul Pap, 2024, 71(6): 2938 doi: 10.1109/TCSI.2024.3373434
[3]
Yun S B, Lee Y. A 5.76 Gb/s 79.7 pJ/b 128 × 32 massive deep-learning uplink MIMO detector in 28nm CMOS technology. 2024 IEEE Asian Solid-State Circuits Conference, 2025: 1
[4]
Kam D, Kong B Y, Lee Y. A 1.1μs 1.56Gb/s/mm2 cost-efficient large-list SCL polar decoder using fully-reusable LLR buffers in 28nm CMOS technology. 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022: 204
[5]
Su B S, Lee C H, Chiueh T D. A 58.6/91.3 pJ/b dual-mode belief-propagation decoder for LDPC and polar codes in the 5G communications standard. IEEE Solid State Circuits Lett, 2022, 5: 98 doi: 10.1109/LSSC.2022.3167423
[6]
Prabhu H, Liu L, Sheikh F, et al. A 1070 pJ/b 169 Mb/s quad-core digital baseband SoC for distributed and cooperative massive MIMO in 28 nm FD-SOI. 2021 Symposium on VLSI Circuits, 2021: 1
[7]
Castañeda O, Benini L, Studer C. A 283 pJ/b 240 Mb/s floating-point baseband accelerator for massive MU-MIMO in 22FDX. ESSCIRC 2022-IEEE 48th European Solid State Circuits Conference (ESSCIRC), 2022: 357
[8]
Zhou H Y, Deng X Y, Cai Y Q, et al. A synchro-set-aided breadth-first sphere decoder for polar-coded MIMO systems. IEEE Trans Signal Process, 2022, 70: 6200 doi: 10.1109/TSP.2022.3229949
[9]
Tang W, Prabhu H, Liu L, et al. A 1.8Gb/s 70.6pJ/b 128 × 16 link-adaptive near-optimal massive MIMO detector in 28nm UTBB-FDSOI. 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 2018: 224
[10]
Jeon C, Castaneda O, Studer C. A 354 Mb/s 0.37 mm2 151 mW 32-user 256-QAM near-MAP soft-input soft-output massive MU-MIMO data detector in 28 nm CMOS. IEEE Solid-State Circuits Lett, 2019, 2(9): 127 doi: 10.1109/LSSC.2019.2935567
[11]
Tang W, Chen C H, Zhang Z Y. A 0.58-mm2 2.76-Gb/s 79.8-pJ/b 256-QAM message-passing detector for a 128 × 32 massive MIMO uplink system. IEEE J Solid State Circuits, 2021, 56(6): 1722 doi: 10.1109/JSSC.2021.3069988
[12]
Lee T, Chen T Y, Liu I H, et al. A 40-nm 131-mW 6.4-Gb/s 256 × 32 multi-user MIMO OTFS detector for next-gen communication systems. IEEE J Solid State Circuits, 2025, 60(9): 3428 doi: 10.1109/JSSC.2025.3550001
[13]
Nadal J, Baghdadi A. Parallel and flexible 5G LDPC decoder architecture targeting FPGA. IEEE Trans Very Large Scale Integr VLSI Syst, 2021, 29(6): 1141 doi: 10.1109/TVLSI.2021.3072866
[14]
Verma A, Shrestha R. High-throughput and hardware-efficient ASIC-chip fabrication of reconfigurable LDPC/polar decoder for mMTC and URLLC 5G-NR applications. IEEE Trans Circuits Syst I Regul Pap, 2024, 71(9): 4284 doi: 10.1109/TCSI.2024.3429174
[15]
Yue Y F, Ajayi T, Liu X Y, et al. A unified forward error correction accelerator for multi-mode turbo, LDPC, and polar decoding. Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design, 2022: 1
[16]
Ji H R, Zhang Y, Sun Y T, et al. UniDec: A unified factor-graph-based decoder fully compatible with 5G NR LDPC/polar codes. IEEE Trans Circuits Syst I Regul Pap, 2025, 72(8): 4235 doi: 10.1109/TCSI.2025.3575534
[17]
Kam D, Yun S B, Choe J, et al. 2.8 a 21.9ns 15.7 Gbps/mm2 (128, 15) boss fec Decoder for 5g/6g urllc Applications. 2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024: 50
[18]
Kwak H Y, Yun D Y, Kim Y, et al. Boosted neural decoders: Achieving extreme reliability of LDPC codes for 6G networks. IEEE J Sel Areas Commun, 2025, 43(4): 1089 doi: 10.1109/JSAC.2025.3531553
[19]
Zhang Y, Zhou W Y, Zhang Y W, et al. BayesBB: A 9.6Gbps 1.61ms configurable all- message-passing baseband-accelerator for B5G/6G cell-free massive-MIMO in 40nm CMOS. 2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024: 48
[20]
Zhang Y, Zhou W Y, Zhang Y W, et al. BayesBB: A 9.6-Gb/s 1.61-ms configurable all-message-passing baseband-accelerator for B5G/6G cell-free massive-MIMO systems. IEEE J Solid State Circuits, 2026, 61(2): 777 doi: 10.1109/JSSC.2025.3571647
Fig. 1.  (Color online) (a) System diagram for baseband signal processing. (b) The architecture and layout of the BsP MIMO detector[2]. (c) Chip micrograph of the deep-learning detector[3]. (d) Chip micrograph and area breakdown of the MIMO-OTFS detector[12].

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Fig. 2.  (Color online) (a) The architecture and layout of the UniDec[16]. (b) Area saving and chip micrograph of the unified FEC[15]. (c) Chip micrograph and area/power breakdown of the BOSS code decoder[17].

DownLoad: Full-Size Img PowerPoint
Fig. 3.  (Color online) Implementation and measurement results of the BayesBB processor, including the chip micrograph in 40 nm CMOS, technical specifications, latency analysis compared to software baselines, and the over-the-air measurement setup[19, 20].

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Table 1.   Comparison of state-of-the-art massive mimo detectors

DetectorStuder
[1]		Zhou
[8]		Tang
[9]		Jeon
[10]		Zhou
[2]		Tang
[11]		Yun
[3]		Lee
[12]
Year20112022201820192024202120242025
Tech node (nm)9040282840402840
AlgorithmMMSEBFSDEPDLAMABPMPDDLMPD
Throughput (Gb/s)0.760.051.800.350.792.765.766.4
Energy efficiency (nJ/b)0.25−0.070.43−0.080.080.02
Core area (mm²)1.50.7820.370.680.586.256.47
DownLoad: CSV

Table 2.   Comparison of state-of-the-art channel-decoders

Detector Kam[4] Verma[14] Su[5] Yue[15] Ji[16] Kam[17]
Year 2022 2024 2022 2022 2025 2024
Tech node [nm] 28 110 40 12 40 28
Algorithm SCL OMSα BP MS BP OMS-BP BOSS
Decoding codes Polar LDPC&Polar LDPC Polar LDPC Polar LDPC Polar BOSS
Throughput (Gb/s) 0.93 3.35 0.92 1.35 0.74 0.95 21.87 10.24 5.8
Energy efficiency (pJ/b) 109.5 59 60.91 91.3 27.4 45.8 6.22 13.28 5.7
Core area (mm²) 0.60 1.96 2.07 − 27.4 45.8
DownLoad: CSV
[1]
Studer C, Fateh S, Seethaler D. ASIC implementation of soft-input soft-output MIMO detection using MMSE parallel interference cancellation. IEEE J Solid State Circuits, 2011, 46(7): 1754 doi: 10.1109/JSSC.2011.2144470
[2]
Zhou W Y, Ji Z H, Tan Z Q, et al. Approximate belief-selective propagation detector for massive MIMO systems. IEEE Trans Circuits Syst I Regul Pap, 2024, 71(6): 2938 doi: 10.1109/TCSI.2024.3373434
[3]
Yun S B, Lee Y. A 5.76 Gb/s 79.7 pJ/b 128 × 32 massive deep-learning uplink MIMO detector in 28nm CMOS technology. 2024 IEEE Asian Solid-State Circuits Conference, 2025: 1
[4]
Kam D, Kong B Y, Lee Y. A 1.1μs 1.56Gb/s/mm2 cost-efficient large-list SCL polar decoder using fully-reusable LLR buffers in 28nm CMOS technology. 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022: 204
[5]
Su B S, Lee C H, Chiueh T D. A 58.6/91.3 pJ/b dual-mode belief-propagation decoder for LDPC and polar codes in the 5G communications standard. IEEE Solid State Circuits Lett, 2022, 5: 98 doi: 10.1109/LSSC.2022.3167423
[6]
Prabhu H, Liu L, Sheikh F, et al. A 1070 pJ/b 169 Mb/s quad-core digital baseband SoC for distributed and cooperative massive MIMO in 28 nm FD-SOI. 2021 Symposium on VLSI Circuits, 2021: 1
[7]
Castañeda O, Benini L, Studer C. A 283 pJ/b 240 Mb/s floating-point baseband accelerator for massive MU-MIMO in 22FDX. ESSCIRC 2022-IEEE 48th European Solid State Circuits Conference (ESSCIRC), 2022: 357
[8]
Zhou H Y, Deng X Y, Cai Y Q, et al. A synchro-set-aided breadth-first sphere decoder for polar-coded MIMO systems. IEEE Trans Signal Process, 2022, 70: 6200 doi: 10.1109/TSP.2022.3229949
[9]
Tang W, Prabhu H, Liu L, et al. A 1.8Gb/s 70.6pJ/b 128 × 16 link-adaptive near-optimal massive MIMO detector in 28nm UTBB-FDSOI. 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 2018: 224
[10]
Jeon C, Castaneda O, Studer C. A 354 Mb/s 0.37 mm2 151 mW 32-user 256-QAM near-MAP soft-input soft-output massive MU-MIMO data detector in 28 nm CMOS. IEEE Solid-State Circuits Lett, 2019, 2(9): 127 doi: 10.1109/LSSC.2019.2935567
[11]
Tang W, Chen C H, Zhang Z Y. A 0.58-mm2 2.76-Gb/s 79.8-pJ/b 256-QAM message-passing detector for a 128 × 32 massive MIMO uplink system. IEEE J Solid State Circuits, 2021, 56(6): 1722 doi: 10.1109/JSSC.2021.3069988
[12]
Lee T, Chen T Y, Liu I H, et al. A 40-nm 131-mW 6.4-Gb/s 256 × 32 multi-user MIMO OTFS detector for next-gen communication systems. IEEE J Solid State Circuits, 2025, 60(9): 3428 doi: 10.1109/JSSC.2025.3550001
[13]
Nadal J, Baghdadi A. Parallel and flexible 5G LDPC decoder architecture targeting FPGA. IEEE Trans Very Large Scale Integr VLSI Syst, 2021, 29(6): 1141 doi: 10.1109/TVLSI.2021.3072866
[14]
Verma A, Shrestha R. High-throughput and hardware-efficient ASIC-chip fabrication of reconfigurable LDPC/polar decoder for mMTC and URLLC 5G-NR applications. IEEE Trans Circuits Syst I Regul Pap, 2024, 71(9): 4284 doi: 10.1109/TCSI.2024.3429174
[15]
Yue Y F, Ajayi T, Liu X Y, et al. A unified forward error correction accelerator for multi-mode turbo, LDPC, and polar decoding. Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design, 2022: 1
[16]
Ji H R, Zhang Y, Sun Y T, et al. UniDec: A unified factor-graph-based decoder fully compatible with 5G NR LDPC/polar codes. IEEE Trans Circuits Syst I Regul Pap, 2025, 72(8): 4235 doi: 10.1109/TCSI.2025.3575534
[17]
Kam D, Yun S B, Choe J, et al. 2.8 a 21.9ns 15.7 Gbps/mm2 (128, 15) boss fec Decoder for 5g/6g urllc Applications. 2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024: 50
[18]
Kwak H Y, Yun D Y, Kim Y, et al. Boosted neural decoders: Achieving extreme reliability of LDPC codes for 6G networks. IEEE J Sel Areas Commun, 2025, 43(4): 1089 doi: 10.1109/JSAC.2025.3531553
[19]
Zhang Y, Zhou W Y, Zhang Y W, et al. BayesBB: A 9.6Gbps 1.61ms configurable all- message-passing baseband-accelerator for B5G/6G cell-free massive-MIMO in 40nm CMOS. 2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024: 48
[20]
Zhang Y, Zhou W Y, Zhang Y W, et al. BayesBB: A 9.6-Gb/s 1.61-ms configurable all-message-passing baseband-accelerator for B5G/6G cell-free massive-MIMO systems. IEEE J Solid State Circuits, 2026, 61(2): 777 doi: 10.1109/JSSC.2025.3571647

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    Received: 11 February 2026 Revised: 16 March 2026 Online: Accepted Manuscript: 28 July 2026Uncorrected proof: 03 September 2026

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      Article Navigation >  Journal of Semiconductors  > 2026  > Uncorrected proof
      Chuan Zhang, Yiwei Zhang, Yu Tian, Kangqi Wu, Kunying Li, Houren Ji, Wenyue Zhou, Yi Zhang, Xiaohu You. Advanced baseband chip designs for B5G and 6G[J]. Journal of Semiconductors, 2026, In Press. doi: 10.1088/1674-4926/26020043 ****C Zhang, Y W Zhang, Y Tian, K Q Wu, K Y Li, H R Ji, W Y Zhou, Y Zhang, and X H You, Advanced baseband chip designs for B5G and 6G[J]. J. Semicond., 2026, 47(9): 090202 doi: 10.1088/1674-4926/26020043
      Citation:
      Chuan Zhang, Yiwei Zhang, Yu Tian, Kangqi Wu, Kunying Li, Houren Ji, Wenyue Zhou, Yi Zhang, Xiaohu You. Advanced baseband chip designs for B5G and 6G[J]. Journal of Semiconductors, 2026, In Press. doi: 10.1088/1674-4926/26020043 ****
      C Zhang, Y W Zhang, Y Tian, K Q Wu, K Y Li, H R Ji, W Y Zhou, Y Zhang, and X H You, Advanced baseband chip designs for B5G and 6G[J]. J. Semicond., 2026, 47(9): 090202 doi: 10.1088/1674-4926/26020043
      shu

      Advanced baseband chip designs for B5G and 6G

      DOI: 10.1088/1674-4926/26020043
      CSTR: 32376.14.1674-4926.26020043

      • Purple Mountain Laboratories, LEADS, Southeast University, Nanjing 211100, China

      More Information
      • Chuan Zhang received the B.E. degree in microelectronics and the M.E. degree in very-large scale integration (VLSI) design from Nanjing University, Nanjing, China, in 2006 and 2009, respectively, and the Ph.D. degree from the Department of Electrical and Computer Engineering, University of Minnesota, Twin Cities (UMN), USA, in 2012.He is currently the Young Chair Professor of Southeast University. He is also with the LEADS, National Mobile Communications Research Laboratory, Frontiers Science Center for Mobile Information Communications and Security of MoE, Quantum Information Center of Southeast University, and the Purple Mountain Laboratories, Nanjing, China. His current research interests are algorithms and implementations for signal processing and communication systems
      • Yiwei Zhang received the M.S. degree in Electronics and Communication Engineering from Anhui University, Hefei, China, in 2012. She is currently pursuing the Ph.D. degree in Electronic and Information Engineering at Southeast University, Nanjing, China. In 2021, she joined the Pervasive Communication Research Center, Purple Mountain Laboratory, Nanjing, China, as an Embedded Development Engineer. Her research interests include massive MIMO, cell-free systems, and 6G baseband signal processing
      • Yu Tian is pursuing her Ph.D. candidate with the School of Information Science and Engineering, Southeast University. She received the B.S. degree from Southeast University, Nanjing, China, in 2021. She is currently focusing on error-correction codes and hardware design
      • Xiaohu You (Fellow, IEEE) received the M.S. and Ph.D. degrees in electrical engineering from Southeast University, Nanjing, China, in 1985 and 1988, respectively. Since 1990, he has been with the National Mobile Communications Research Laboratory, Southeast University, where he is currently the Director and a full Professor. He is an academician of the Chinese Academy of Sciences. He has long been engaged in teaching, scientific research, and organizational management of mobile communication systems, and made important contributions to the development of China’s 3G, 4G and 5G mobile communications. From 1999 to 2002, he was a Principal Expert of the C3G Project, responsible for organizing China's 3G Mobile Communications Research and Development Activities. From 2001 to 2006, he was a Principal Expert of the China National 863 Beyond 3G FuTURE Project. Since 2013, he has been a Principal Investigator of the China National 863 5G Project. As the first recipient, he won the 1st Class National Technological Invention Award, the 2nd Class National Science and Technology Progress Award, Tan Kah Kee Science Award, and other important awards.His research interests include mobile communication systems, and signal processing and its applications. He has contributed over 200 IEEE journal articles and 2 books in the areas of adaptive signal processing and neural networks, and their applications to communication systems. Dr. You was elected as IEEE Fellow for his contributions to the development of mobile communications in China in 2011. He served as the General Chair of the IEEE Wireless Communications and Networking Conference 2013, the IEEE Vehicular Technology Conference 2016, and the IEEE International Conference on Communications 2019. He is the Secretary-General of the FuTURE Forum and the Vice-Chair of the China IMT-2020 Promotion Group and the China National Mega Project on New Generation Mobile Network
      • Corresponding author: chzhang@seu.edu.cn; xhyu@seu.edu.cn
      • Received Date: 2026-02-11
      • Revised Date: 2026-03-16
        • Available Online: 2026-07-28

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