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Transmitter-side FFE techniques for switching jitter compensation in high-speed interfaces

Sihan Li, Hongzhi Wu, Xiaohu Fang, Qiancheng Zhao, Junmin Jiang and Quan Pan

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 Corresponding author: Quan Pan, panq@sustech.edu.cn

DOI: 10.1088/1674-4926/26020067CSTR: 32376.14.1674-4926.26020067

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[1]
Kim J, Kundu S, Balankutty A, et al. A 224-Gb/s DAC-based PAM-4 quarter-rate transmitter with 8-tap FFE in 10-nm FinFET. IEEE J Solid State Circuits, 2022, 57(1): 6C doi: 10.1109/JSSC.2021.3108969
[2]
Groen E, Boecker C, Hossain M, et al. 6.3 a 10-to-112Gb/s DSP-DAC-based transmitter with 1.2Vppd output swing in 7nm FinFET. 2020 IEEE International Solid- State Circuits Conference (ISSCC), 2020: 120
[3]
Sheng K, Gai W X, Feng Z Z, et al. 6.7 a 128Gb/s PAM-4 transmitter with programmable-width pulse generator and pattern-dependent pre-emphasis in 28nm CMOS. 2023 IEEE International Solid-State Circuits Conference (ISSCC), 2023: 120
[4]
Peng P J, Chen Y T, Lai S T, et al. A 112-Gb/s PAM-4 voltage-mode transmitter with four-tap two-step FFE and automatic phase alignment techniques in 40-nm CMOS. IEEE J Solid State Circuits, 2021, 56(7): 2123 doi: 10.1109/JSSC.2020.3038818
[5]
Toprak-Deniz Z, Proesel J E, Bulzacchelli J F, et al. A 128-Gb/s 1.3-pJ/b PAM-4 transmitter with reconfigurable 3-tap FFE in 14-nm CMOS. IEEE J Solid State Circuits, 2020, 55(1): 19 doi: 10.1109/JSSC.2019.2939081
[6]
Zheng X Q, Ding H, Zhao F, et al. A 50–112-Gb/s PAM-4 transmitter with a fractional-spaced FFE in 65-nm CMOS. IEEE J Solid State Circuits, 2020, 55(7): 1864 doi: 10.1109/JSSC.2020.2987712
[7]
Han J, Sutardja N, Lu Y, et al. Design techniques for a 60-Gb/s 288-mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65-nm CMOS technology. IEEE J Solid State Circuits, 2017, 52(12): 3474 doi: 10.1109/JSSC.2017.2740268
[8]
Wang Z K, Choi M, Lee K, et al. An output bandwidth optimized 200-Gb/s PAM-4 100-Gb/s NRZ transmitter with 5-tap FFE in 28-nm CMOS. IEEE J Solid State Circuits, 2022, 57(1): 21 doi: 10.1109/JSSC.2021.3109562
[9]
He Y K, Yuan Z, Wang K N, et al. A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver with 1/4 rate reconfigurable 4-tap FFE and half-rate slicer in a 28-nm CMOS. J Semicond, 2024, 45(6): 062204 doi: 10.1088/1674-4926/24010001
[10]
Wu H Z, Cheng X X, Wu W T, et al. A 128-Gb/s PAM-4 transmitter with edge-boosting pulse generator and pre-emphasis asymmetric fractional-spaced FFE in 28-nm CMOS. IEEE J Solid State Circuits, 2026, 61(1): 293 doi: 10.1109/JSSC.2025.3557781
[11]
Wu H Z, Wu W T, Zhong L P, et al. A 2 x 24Gb/s single-ended transceiver with channel-independent encoder-based crosstalk cancellation in 28nm CMOS. 2023 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2023: 1
[12]
Wu W T, Wu H Z, Zhong L P, et al. 13.5 a 64Gb/s/pin PAM4 single-ended transmitter with a merged pre-emphasis capacitive-peaking crosstalk-cancellation scheme for memory interfaces in 28nm CMOS. 2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024: 240
[13]
Momtaz A, Green M M. An 80 mW 40 Gb/s 7-Tap T/2-Spaced Feed-Forward Equalizer in 65 nm CMOS. IEEE J Solid State Circuits, 2010, 45(3): 629 doi: 10.1109/JSSC.2009.2039268
[14]
Dickson T O, Ainspan H A, Meghelli M. 6.5 A 1.8pJ/b 56Gb/s PAM-4 transmitter with fractionally spaced FFE in 14nm CMOS. 2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017: 118
[15]
Wang K N, Tang R J, Xiang S Y, et al. A 0.92-pJ/b 112-Gb/s PAM-4 transmitter with bandwidth and linearity enhanced quasi-voltage-mode driver and reconfigurable three-tap T/2–T variable fractional-spaced FFE in 28-nm CMOS. IEEE Trans Circuits Syst I, 2025, 72(6): 2664 doi: 10.1109/tcsi.2025.3558331
[16]
Jin J, Lee S M, Min K, et al. A 4nm 16Gb/s/pin single-ended PAM4 parallel transceiver with switching-jitter compensation and transmitter optimization. 2023 IEEE International Solid-State Circuits Conference (ISSCC), 2023: 1
[17]
Wu H Z, Wu W T, Zhong L P, et al. A 128Gb/s PAM-4 transmitter with edge-boosting pulse generator and pre-emphasis asymmetric fractional-spaced FFE in 28nm CMOS. 2024 IEEE Custom Integrated Circuits Conference (CICC), 2024: 1
[18]
Kim S, Sim J, Choi Y, et al. Single-ended PAM-4 transmitters with data bus inversion and ZQ calibration for high-speed memory interfaces. IEEE J Solid State Circuits, 2024, 59(10): 3432 doi: 10.1109/JSSC.2024.3403149
[19]
Ye B Y, Sheng K, Gai W X, et al. A 2.29-pJ/b 112-Gb/s wireline transceiver with RX four-tap FFE for medium-reach applications in 28-nm CMOS. IEEE J Solid State Circuits, 2023, 58(1): 19 doi: 10.1109/JSSC.2022.3223052
[20]
Wu H Z, Cheng X X, Zhang Y Y, et al. A 72Gb/s/pin single-ended driver-cooperative coded PAM3 transceiver with asymmetric data-dependent equalization and bias-peaking for chiplets and memory interfaces. 2026 IEEE International Solid-State Circuits Conference (ISSCC), 2026: 624
Fig. 1.  (Color online) (a) Architecture of DSP-based TX and analog-based TX. (b) Architectures of analog UI-spaced FFE, segment UI-spaced FFE and FS-FFE. (c) TX FFE and driver architecture proposed in Ref.[9] (d) NRZ eye, PAM-4 eye’s SWJ and PAM-4 eye’s SWJ with AFS-FFE. (e) TX architecture proposed in Ref.[6] (f) TX architecture proposed in Ref.[15]

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Fig. 2.  (Color online) (a) TX architecture proposed in Ref.[10] (b) Schematic of the proposed AFS-FFE and FS-FFE signal synthesis process and its relevant details. (c) Schematic of the driver bundle with proposed edge-boosting pulse generator. (d) Schematic of the edge-boosting pulse generator and its timing diagram. (e) Measured 112-Gb/s PAM-4 eye without FFE, 112-Gb/s PAM-4 eye with UI-spaced FFE, 112-Gb/s PAM-4 eye with AFS-FFE and 128-Gb/s PAM-4 eye with AFS-FFE. (f) Die photo. (g) Power breakdown of the TX.

DownLoad: Full-Size Img PowerPoint
[1]
Kim J, Kundu S, Balankutty A, et al. A 224-Gb/s DAC-based PAM-4 quarter-rate transmitter with 8-tap FFE in 10-nm FinFET. IEEE J Solid State Circuits, 2022, 57(1): 6C doi: 10.1109/JSSC.2021.3108969
[2]
Groen E, Boecker C, Hossain M, et al. 6.3 a 10-to-112Gb/s DSP-DAC-based transmitter with 1.2Vppd output swing in 7nm FinFET. 2020 IEEE International Solid- State Circuits Conference (ISSCC), 2020: 120
[3]
Sheng K, Gai W X, Feng Z Z, et al. 6.7 a 128Gb/s PAM-4 transmitter with programmable-width pulse generator and pattern-dependent pre-emphasis in 28nm CMOS. 2023 IEEE International Solid-State Circuits Conference (ISSCC), 2023: 120
[4]
Peng P J, Chen Y T, Lai S T, et al. A 112-Gb/s PAM-4 voltage-mode transmitter with four-tap two-step FFE and automatic phase alignment techniques in 40-nm CMOS. IEEE J Solid State Circuits, 2021, 56(7): 2123 doi: 10.1109/JSSC.2020.3038818
[5]
Toprak-Deniz Z, Proesel J E, Bulzacchelli J F, et al. A 128-Gb/s 1.3-pJ/b PAM-4 transmitter with reconfigurable 3-tap FFE in 14-nm CMOS. IEEE J Solid State Circuits, 2020, 55(1): 19 doi: 10.1109/JSSC.2019.2939081
[6]
Zheng X Q, Ding H, Zhao F, et al. A 50–112-Gb/s PAM-4 transmitter with a fractional-spaced FFE in 65-nm CMOS. IEEE J Solid State Circuits, 2020, 55(7): 1864 doi: 10.1109/JSSC.2020.2987712
[7]
Han J, Sutardja N, Lu Y, et al. Design techniques for a 60-Gb/s 288-mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65-nm CMOS technology. IEEE J Solid State Circuits, 2017, 52(12): 3474 doi: 10.1109/JSSC.2017.2740268
[8]
Wang Z K, Choi M, Lee K, et al. An output bandwidth optimized 200-Gb/s PAM-4 100-Gb/s NRZ transmitter with 5-tap FFE in 28-nm CMOS. IEEE J Solid State Circuits, 2022, 57(1): 21 doi: 10.1109/JSSC.2021.3109562
[9]
He Y K, Yuan Z, Wang K N, et al. A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver with 1/4 rate reconfigurable 4-tap FFE and half-rate slicer in a 28-nm CMOS. J Semicond, 2024, 45(6): 062204 doi: 10.1088/1674-4926/24010001
[10]
Wu H Z, Cheng X X, Wu W T, et al. A 128-Gb/s PAM-4 transmitter with edge-boosting pulse generator and pre-emphasis asymmetric fractional-spaced FFE in 28-nm CMOS. IEEE J Solid State Circuits, 2026, 61(1): 293 doi: 10.1109/JSSC.2025.3557781
[11]
Wu H Z, Wu W T, Zhong L P, et al. A 2 x 24Gb/s single-ended transceiver with channel-independent encoder-based crosstalk cancellation in 28nm CMOS. 2023 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2023: 1
[12]
Wu W T, Wu H Z, Zhong L P, et al. 13.5 a 64Gb/s/pin PAM4 single-ended transmitter with a merged pre-emphasis capacitive-peaking crosstalk-cancellation scheme for memory interfaces in 28nm CMOS. 2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024: 240
[13]
Momtaz A, Green M M. An 80 mW 40 Gb/s 7-Tap T/2-Spaced Feed-Forward Equalizer in 65 nm CMOS. IEEE J Solid State Circuits, 2010, 45(3): 629 doi: 10.1109/JSSC.2009.2039268
[14]
Dickson T O, Ainspan H A, Meghelli M. 6.5 A 1.8pJ/b 56Gb/s PAM-4 transmitter with fractionally spaced FFE in 14nm CMOS. 2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017: 118
[15]
Wang K N, Tang R J, Xiang S Y, et al. A 0.92-pJ/b 112-Gb/s PAM-4 transmitter with bandwidth and linearity enhanced quasi-voltage-mode driver and reconfigurable three-tap T/2–T variable fractional-spaced FFE in 28-nm CMOS. IEEE Trans Circuits Syst I, 2025, 72(6): 2664 doi: 10.1109/tcsi.2025.3558331
[16]
Jin J, Lee S M, Min K, et al. A 4nm 16Gb/s/pin single-ended PAM4 parallel transceiver with switching-jitter compensation and transmitter optimization. 2023 IEEE International Solid-State Circuits Conference (ISSCC), 2023: 1
[17]
Wu H Z, Wu W T, Zhong L P, et al. A 128Gb/s PAM-4 transmitter with edge-boosting pulse generator and pre-emphasis asymmetric fractional-spaced FFE in 28nm CMOS. 2024 IEEE Custom Integrated Circuits Conference (CICC), 2024: 1
[18]
Kim S, Sim J, Choi Y, et al. Single-ended PAM-4 transmitters with data bus inversion and ZQ calibration for high-speed memory interfaces. IEEE J Solid State Circuits, 2024, 59(10): 3432 doi: 10.1109/JSSC.2024.3403149
[19]
Ye B Y, Sheng K, Gai W X, et al. A 2.29-pJ/b 112-Gb/s wireline transceiver with RX four-tap FFE for medium-reach applications in 28-nm CMOS. IEEE J Solid State Circuits, 2023, 58(1): 19 doi: 10.1109/JSSC.2022.3223052
[20]
Wu H Z, Cheng X X, Zhang Y Y, et al. A 72Gb/s/pin single-ended driver-cooperative coded PAM3 transceiver with asymmetric data-dependent equalization and bias-peaking for chiplets and memory interfaces. 2026 IEEE International Solid-State Circuits Conference (ISSCC), 2026: 624

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    Received: 27 February 2026 Revised: 23 May 2026 Online: Accepted Manuscript: 28 June 2026

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      Article Navigation >  Journal of Semiconductors  > 2026  > Accepted Manuscript
      Sihan Li, Hongzhi Wu, Xiaohu Fang, Qiancheng Zhao, Junmin Jiang, Quan Pan. Transmitter-side FFE techniques for switching jitter compensation in high-speed interfaces[J]. Journal of Semiconductors, 2026, In Press. doi: 10.1088/1674-4926/26020067 ****S H Li, H Z Wu, X H Fang, Q C Zhao, J M Jiang, and Q Pan, Transmitter-side FFE techniques for switching jitter compensation in high-speed interfaces[J]. J. Semicond., 2026, accepted doi: 10.1088/1674-4926/26020067
      Citation:
      Sihan Li, Hongzhi Wu, Xiaohu Fang, Qiancheng Zhao, Junmin Jiang, Quan Pan. Transmitter-side FFE techniques for switching jitter compensation in high-speed interfaces[J]. Journal of Semiconductors, 2026, In Press. doi: 10.1088/1674-4926/26020067 ****
      S H Li, H Z Wu, X H Fang, Q C Zhao, J M Jiang, and Q Pan, Transmitter-side FFE techniques for switching jitter compensation in high-speed interfaces[J]. J. Semicond., 2026, accepted doi: 10.1088/1674-4926/26020067
      shu

      Transmitter-side FFE techniques for switching jitter compensation in high-speed interfaces

      DOI: 10.1088/1674-4926/26020067
      CSTR: 32376.14.1674-4926.26020067

      • School of Microelectronics, Southern University of Science and Technology, Shenzhen 518055, China

      More Information
      • Sihan Li is currently an undergraduate student in the School of Microelectronics, Southern University of Science and Technology (SUSTech), Shenzhen, China. Her research interests include high-speed transceivers and optical interconnects
      • Hongzhi Wu (Member, IEEE) received the B.S. degree in communication engineering from the University of Electronic Science and Technology of China (UESTC), Chengdu, China, in 2020, and the Ph.D. degree from the Southern University of Science and Technology (SUSTech), Shenzhen, China, in 2025. His research interests include high-speed wireline transceivers and low-power equalizers
      • Xiaohu Fang (Senior Member, IEEE) received the B.Eng. and M.Eng. degrees in electronic science and technology from the Huazhong University of Science and Technology, Wuhan, Hubei, China, in 2008 and 2011, respectively, and the Ph.D. degree in electronic engineering from The Chinese University of Hong Kong, Hong Kong, in 2015. He is currently an Assistant Professor with the School of Micro-Electronics, Southern University of Science and Technology, Shenzhen, China. His current research interests include the development of highly efficient radio front-end techniques for 5G communications and the design of hybrid and GaN-integrated high-efficiency and high-linearity power amplifiers and associated linearization methods
      • Qiancheng Zhao (Senior Member, IEEE) received the B.S. degree in the Department of Optical Engineering, Zhejiang University, Hangzhou, China, in 2012, and the Ph.D degree in the Department of Electrical Engineering and Computer Science, University of California, Irvine (UCI), CA, USA, in 2017. He worked in Apple Inc. as a signal integrity engineer since 2017, and then in the University of California, Santa Barbara as a Postdoctoral Researcher since 2019. In 2021, he joined the School of Microelectronics, Southern University of Science and Technology (SUSTech), Shenzhen, China, where he is currently an Assistant Professor. His current research interests include integrated photonic circuits on chips, such as low-loss optical waveguide devices and nonlinear integrated photonic devices. He has published over 70 papers in international journals and conferences, such as Nature Communications, Optica, Advanced Optical Materials, Nanophotonics, ACS Photonics, APL Photonics
      • Junmin Jiang (Member, IEEE) received the B.Eng. degree in electronic and information engineering from Zhejiang University, Hangzhou, China, in 2011, and the Ph.D. degree in electronic and computer engineering from Hong Kong University of Science and Technology (HKUST), Hong Kong, in 2017. He was a Visiting Scholar with the State Key Laboratory of AMSV, University of Macau, Macau, China, in 2015, and a Post-Doctoral Fellow with HKUST, in 2017. He was an Analog Design Engineer with Kilby Labs Silicon Valley, Texas Instruments, Santa Clara, CA, USA, from 2018 to 2021. In 2021, he joined the Southern University of Science and Technology (SUSTech), Shenzhen, China, where he is currently an Associate Professor. His current research interests include power management IC design, especially in switched-mode power converter design. Prof. Jiang serves as an Associate Editor and Guest Editor for IEEE Transactions on Circuits and Systems II: Express Briefs, and the Review Committee Member of IEEE ISCAS from 2021 to 2024. He was a recipient of the Analog Devices Inc. (ADI) Outstanding Student Designer Award in 2015, the Solomon Systech Scholarship in 2017, the IEEE Solid-State Circuits Society (SSCS) Pre-Doctoral Achievement Award 2016–2017, the ASP-DAC University LSI Design Contest Special Feature Award in 2018, Texas Instruments Patent Awards in 2019–2020, the NSFC Excellent Young Scientists Fund (Overseas) in 2022, and the ASP-DAC Design Contest Best Design Award in 2026
      • Quan Pan (Senior Member, IEEE) received B.S. degree in electrical engineering (EE) from the University of Science and Technology of China (USTC), Hefei, China, in 2005, and the Ph.D. degree in electronics and computer engineering (ECE) from The Hong Kong University of Science and Technology (HKUST), Hong Kong, China, in 2014. From 2014 to 2018, he was a Senior Staff Engineer at one Silicon Valley start-up company, working on 400-GbE high-speed SerDes. He joined the School of Microelectronics, Southern University of Science and Technology (SUSTech), Shenzhen, China, in 2018, as an Assistant Professor, where he is currently a Full Professor with early promotions. He has contributed more than 90 peer-reviewed articles. His research interests include high-speed optical and wireline circuit design. Dr. Pan received the 2017 Outstanding Young Author Award of IEEE Circuits and System Society. He serves as an Active Reviewer for many international journals, including JSSC, TCAS, TVLSI, JLT, PTL, and JoS
      • Corresponding author: panq@sustech.edu.cn
      • Received Date: 2026-02-27
      • Revised Date: 2026-05-23
        • Available Online: 2026-06-28

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