From device non-idealities to computation accuracy: A cross-layer review of error mechanisms and mitigation in analog in-memory computing

Zeying Ding; Yantong Di; Haoran Du; Haoran Chen; Yaoru Hou; Bo Liu; Hao Cai

doi:10.1088/1674-4926/26060006

J. Semicond. > Just Accepted

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From device non-idealities to computation accuracy: A cross-layer review of error mechanisms and mitigation in analog in-memory computing

Zeying Ding¹, Yantong Di¹, Haoran Du¹, Haoran Chen¹, Yaoru Hou^2,, Bo Liu¹ and Hao Cai^1,

+ Author Affiliations

1. School of Integrated Circuits, Southeast University, Nanjing 210096, China
2. Dept. of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, Hong Kong 999077, China

Author Bio:

Zeying Ding received the B.S. degree from Jilin University, Changchun, China, in 2021, and the M.E. degree from the University of Chinese Academy of Sciences, Beijing, China, in 2024. She is currently pursuing the Ph.D. degree with the School of Integrated Circuits, Southeast University, Nanjing, China. Her research interests include magnetic random-access memory circuit design, MRAM-based in-memory computing, and neuromorphic computing circuits.

Yantong Di received the B.Eng. degree in electronic science and technology from Southeast University, Nanjing, China, in 2022, and the M.Sc. degree in IC design engineering from The Hong Kong University of Science and Technology, Hong Kong, China, in 2024. She is currently pursuing the Ph.D. degree with the School of Integrated Circuits, Southeast University, Nanjing, China. Her research interests include MRAM device modeling and design-technology co-optimization, radiation-hardened circuit design, and MRAM-based computing.

Haoran Du received the B.S. degree in physics from University of Washington, Seattle, USA in 2021, and M.S. degree in microelectronics from Newcastle University, Newcastle upon Tyne, U.K. in 2022. He is currently pursuing the Ph.D. degree in integrated circuit engineering with Southeast University, Nanjing, China. His research interests include circuit design of MRAM design, non-volatile computing in memory, and design-technology co-optimization.

Haoran Chen received the B.Eng. degree from Shandong University, Weihai, China, in 2025. He is currently pursuing the M.Eng. degree at Southeast University. His research interests include computer architecture and memory systems.

Yaoru Hou received the B.S. and M.S. degrees from Southeast University, Nanjing, China, in 2016 and 2023, respectively. He is currently pursuing the Ph.D. degree in Electronic and Computer Engineering at the Hong Kong University of Science and Technology. His research interests include MTJ device modeling, MRAM circuit design, and spintronic-based unconventional AI accelerators. He has authored or co-authored five papers in major international conferences, including IEDM, ISSCC, and CICC. He has participated in five chip tape-outs involving CMOS-integrated STT-, SOT-, and VCMA-MTJ technologies targeting MRAM commercialization.

Bo Liu received the B.S. and Ph.D. degrees in electronic science and engineering from Southeast University, Nanjing, China, in 2006 and 2013, respectively. He is currently an Associate Professor with the National ASIC System Engineering Research Center, School of Integrated Circuits, Southeast University. His research is supported by the National Natural Science Foundation, the National Science and Technology Major Project, and the National Key Research and Development Program. He has authored or co-authored three book chapters and more than 60 scientific papers, including Nature Electronics, MICRO, ISSCC, DAC, TCAS-I,TCAS-II, TCAD, and IEEE Circuits and Systems Magazine. He holds one U.S. patent and more than 30 Chinese patents. His research interests include chip architecture design, reconfigurable computing, and approximate computing.

Hao Cai received the master’s degree in electrical engineering from Lund University, Sweden, in 2009, and the Ph.D. degree in electrical engineering from Télécom ParisTech, France, in 2013. From 2013 to 2017, he was with Université Paris-Saclay, France, working on reliable low-power integrated circuit design. In 2018, he joined the National ASIC System Engineering Center, Southeast University, Nanjing, China, where he is currently a Professor. In 2019, he was with Semiconductor Manufacturing International Corporation (SMIC), working on high-density FinFET MRAM. He is also working on low-power MRAM design and device-circuit design interaction. He has been serving on IEEE-CAS technical committees and as a conference TPC member for DAC, GLSVLSI, Nanoarch, ESREF, and NEWCAS. He has authored or co-authored over 120 scientific articles and received several conference best paper awards.

Corresponding author: Yaoru Hou, hao.cai@seu.edu.cn; Hao Cai, yhouas@connect.ust.hk

DOI: 10.1088/1674-4926/26060006CSTR: 32376.14.1674-4926.26060006

Abstract: Analog in-memory computing (AIMC) has attracted significant attention as an energy-efficient computing paradigm for data-intensive workloads. However, its practical deployment is fundamentally limited by various non-idealities across multiple abstraction levels, which degrade computational accuracy and reliability. This paper presents a comprehensive review of non-idealities in AIMC systems from a cross-layer perspective. A common computational representation is introduced to illustrate how diverse physical non-idealities may manifest as weight perturbations, multiplicative distortions, nonlinear transfer effects, additive errors, and quantization or accumulation errors. From this perspective, we review design techniques across device, array, circuit, data-conversion, and system levels, and discuss how errors are generated, transformed, and accumulated throughout the computation flow. Furthermore, algorithm-hardware co-design strategies are discussed as an effective approach to mitigate cross-layer errors and enhance system robustness. By providing a structured overview of error generation, transformation, and propagation, this work highlights the importance of cross-layer co-design and offers insights into the design trade-offs among accuracy, efficiency, and scalability in AIMC systems.

Keywords: analog in-memory computing (AIMC), cross-layer perspective, non-idealities, error propagation, algorithm-hardware co-design

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Fig. 1. (Color online) Comparison between conventional von Neumann and IMC architectures. (a) Conventional von Neumann architecture with frequent data movement between processing units and memory, causing the memory wall bottleneck. (b) IMC-based processor composed of multiple computing tiles, where data storage and computation are tightly integrated, reducing data movement and improving energy efficiency.

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Fig. 2. (Color online) Cross-layer generation and propagation of AIMC errors. (a) Device-level non-idealities affecting weight representation. (b) Array-level distortions caused by interconnect and parasitic effects. (c) Circuit-level sensing and signal-processing errors. (d) Conversion errors arising from sampling, quantization, and nonlinearity. (e) System-level redistribution, accumulation, and propagation of lower-level errors through mapping, multi-cycle execution, and layer-wise network computation.

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Fig. 3. Device-level variability mitigation techniques in AIMC. (a) Iterative write-verify programming that adaptively applies SET or RESET pulses until the measured conductance reaches the target range^[19]. (b) Dual-threshold write-verify circuit using two VSAs to determine whether the programmed resistance lies within the target window^[32].

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Fig. 4. (Color online) Array-level techniques for mitigating non-idealities and improving computation accuracy in AIMC. (a) Bitline current modulation based on bit significance prior to accumulation^[34]. (b) Partitioning of large arrays into smaller computing units with embedded local conversion to improve scalability and signal integrity^[23]. (c) In situ calibration using intrinsic reference currents for adaptive compensation of spatial variations and near-far effects, with improved linearity after compensation^[37]. (d) Even-odd dual-channel organization and two-channel accumulation, which reduce the load on each bitline and enable parallel processing of the even and odd channels for improved bandwidth and throughput^[38].

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Fig. 5. (Color online) Representative reference-adaptive and differential sensing techniques for robust IMC readout. (a) Pinatubo current-sense amplifier with operation- and row-count-dependent reference selection for multi-row Boolean evaluation^[41]. (b) Complementary 2T2R RRAM bit-cell with an XNOR-capable differential precharge sense amplifier, providing reference-free sensing and reduced bit error rate without ECC^[22].

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Fig. 6. (Color online) Representative signal-amplification techniques for enhancing sensing margin in AIMC. (a) Triple-margin current-mode sense amplifier combining threshold-voltage sampling, overdrive-voltage sampling and capacitive coupling, and current-difference amplification to enlarge the input sensing margin^[34]. (b) Differential cascode G-to-I converter using cascode amplification, closed-loop feedback, auto-zeroing, and current copying to convert MRAM conductance differences into output currents while rejecting power-supply noise^[44]. (c) Voltage-swing-remapping VSA using coarse-fine sensing and capacitive voltage remapping to achieve a 2× margin enhancement before fine quantization^[45].

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Fig. 7. (Color online) Representative circuit techniques for linearity enhancement and computation-mode transformation in AIMC. (a) Feedback-assisted current mirror that stabilizes the capacitor-charging current as the output voltage increases^[46]. (b) Binary-weighted PMOS current mirrors with 8:4:2:1 scaling for multi-bit dot-product accumulation^[48]. (c) 2T2R voltage-division computing that directly maps MAC values to the CSL voltage without current-to-voltage conversion^[20]. (d) Input-aware bitline-current control and active feedback that linearize the readout voltage under accumulated HRS currents^[31]. (e) Fully parallel capacitive-coupling computation based on MBL precharge and charge redistribution^[50].

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Fig. 8. (Color online) Calibration and compensation techniques for mitigating circuit-level non-idealities in analog IMC. (a) Array-wide PMOS body-bias calibration that shifts V_RBL toward the target VDD/2 operating point for a zero XAC output^[51]. (b) Background online HRS read-disturb detection that monitors V_RBL and triggers reset recovery when resistance drift exceeds the detection threshold^[31]. (c) In-array midpoint-conductance auto-zeroing that stores cascode- and amplifier-bias points on capacitors to mitigate channel offsets and SL-voltage variation^[43]. (d) Two-phase offset-compensating current sensing that samples circuit offset during auto-zeroing and suppresses static ADC-column mismatch during evaluation^[16].

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Fig. 9. (Color online) ADC architectures and calibration techniques for AIMC interfaces. (a) Capacitor-reconfigured CIM that reuses the compute capacitor array as a 10-bit C-DAC for SAR conversion, reducing the area overhead of high-resolution readout^[66]. (b) Analog-storage quantizer that counts full-scale charge events during accumulation and quantizes the residual capacitor voltage using a SAR ADC, supporting long accumulation with an output ratio of 1^[67]. (c) APoT ADC that combines two PoT-weighted CAP-DAC outputs through charge sharing to generate nonuniform reference levels with finer resolution near densely distributed outputs^[68]. (d) Dynamic-scaling ADC using matched compute and sensing capacitors and segmented charge-line scaling to adapt the sensing range and resolution across weight-bit positions^[69]. (e) Split-DAC SAR ADC with a half-LSB-weighted offset-trimming capacitor bank for intrinsic-offset and data-dependent$ {I}_{\text{OFF}} $ compensation^[35]. (f) On-chip reference array using fixed and tunable RRAM cells to generate independently calibrated thresholds for each 3-bit flash ADC^[32].

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Fig. 10. (Color online) Representative multibit input-encoding techniques for AIMC. (a) Eight-bit segmentation-buffer D2A using a shared 4-bit RDAC and 16C/1C capacitive voltage addition to convert each word-wise input in a single operation^[47]. (b) Single-pulse-width GBL DAC that maps the digital input code to a proportional charging duration using shared timing signals, improving linearity and mismatch tolerance^[52]. (c) Charge-recycling DAC that redistributes residual capacitor charge through a shared short line between successive MAC operations to reduce capacitive driving energy^[72].

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Fig. 11. (Color online) Time-domain conversion techniques for AIMC. (a) Dynamic differential-reference TDC that compares selected MAC-output edges with configurable main and bias references, converts the relative delays into differential and bias MAC values, and reconstructs the partial MAC result with a shortened sampling period^[76]. (b) Low-dMACV-aware recursive TDC using separate 3-bit Flash-TDC paths for LSB and MSB sensing, dMACV-zone detection, and conditional bypass of MSB sensing to reduce readout energy and area overhead^[77].

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Fig. 12. (Color online) Mixed-signal and ADC-free computation techniques in AIMC. (a) Analog inter-layer dataflow using ping-pong analog memories to store and forward intermediate activations, with DAC and ADC operations confined to the first-layer input and final-layer output, respectively^[79]. (b) Reconfigurable analog activation circuitry using segmented Taylor-approximation circuits to implement nonlinear functions without intermediate AD/DA conversion^[80]. (c) Stacked reverse-charge quantization readout using capacitor stacks and comparator-counter-based coarse quantization, followed by a single SAR-ADC operation for fine quantization^[81]. (d) ADC-free 3T2R readout in which pull-up/pull-down competition produces a voltage-division result that is directly digitized by the output-inverter switching threshold^[82].

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Fig. 13. (Color online) System-level optimization techniques for improving accuracy and efficiency in AIMC. (a) Asymmetric group-modulated input and hybrid-precision readout that partition an 8-bit input into 2-bit, 3-bit, and 3-bit groups, allocate longer evaluation and full-precision sensing to the MSB group, and reconstruct the partial results through digital shift-and-add^[91]. (b) Hybrid precision mapping that allocates MSBs to reliable storage modes and LSBs to high-density configurations^[45]. (c) Delta-sigma CIM dataflow in which delta-input holders encode changes between consecutive inputs, capacitor-coupled arrays compute delta MVMs, LSB-first ADCs digitize the near-zero-mean outputs, and sigma adders recover the normal partial sums^[70].

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Fig. 14. (Color online) Algorithm-hardware co-design techniques for improving robustness under hardware non-idealities. (a) Nonideality-aware training that models read nonlinearity, mismatch, variation, and noise^[101]. (b) ADC-less hybrid CIM that processes quantized partial sums and scale factors through digital-CIM add/subtract operations^[104]. (c) Pipelined DSCONV layer fusion with on-chip buffering of intermediate activations^[68].

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Fig. 15. (Color online) Calibration and post-training compensation techniques for AIMC. (a) Device-variation-aware adaptive quantization using conductance-shift sensing and a device-specific LUT for off-chip fine-tuning^[25]. (b) Multi-stage reference-voltage, offset, macro-gain, and group-gain calibration, with actual network weights used for macro-gain tuning^[108]. (c) Stress-aware dynamic boundary adaptation using row-wise counters and LUT-controlled pull-up configurations to compensate for RRAM state drift^[109].

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Table 1. Taxonomy of cross-layer optimization techniques for AIMC

Layer	Error mechanisms and effects	Representative techniques	Optimization target	Trade-offs
Device	Conductance variation, drift, stochastic switching	Device engineering, multi-level programming, verify-and-write	Improve weight precision and retention	Write latency, endurance overhead
Array	IR drop, sneak current, parasitic coupling	Array partitioning, compensation mapping, line optimization	Reduce spatial computation distortion	Area and routing overhead
Circuit	Sensing offset, noise, PVT variation	Calibration circuits, reference optimization, robust sensing	Improve sensing robustness and read margin	Power and design complexity
Data conversion	Quantization noise, ADC/DAC nonlinearity	Low-precision ADC, adaptive conversion, mixed-signal encoding	Reduce conversion energy and quantization error	Accuracy degradation
System	Error redistribution and accumulation	Error-aware mapping, adaptive scheduling	Improve end-to-end accuracy	Scheduling complexity
Algorithm	Sensitivity to hardware perturbations	QAT, noise injection, hardware-aware training	Improve robustness to hardware errors	Retraining cost

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Received: 02 June 2026 Revised: 01 August 2026 Online: Accepted Manuscript: 10 September 2026

Article Navigation > Journal of Semiconductors > 2026 > Accepted Manuscript

Zeying Ding, Yantong Di, Haoran Du, Haoran Chen, Yaoru Hou, Bo Liu, Hao Cai. From device non-idealities to computation accuracy: A cross-layer review of error mechanisms and mitigation in analog in-memory computing[J]. Journal of Semiconductors, 2026, In Press. doi: 10.1088/1674-4926/26060006 ****Z Y Ding, Y T Di, H R Du, H R Chen, Y R Hou, B Liu, and H Cai, From device non-idealities to computation accuracy: A cross-layer review of error mechanisms and mitigation in analog in-memory computing[J]. J. Semicond., 2026, accepted doi: 10.1088/1674-4926/26060006

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Z Y Ding, Y T Di, H R Du, H R Chen, Y R Hou, B Liu, and H Cai, From device non-idealities to computation accuracy: A cross-layer review of error mechanisms and mitigation in analog in-memory computing[J]. J. Semicond., 2026, accepted doi: 10.1088/1674-4926/26060006

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From device non-idealities to computation accuracy: A cross-layer review of error mechanisms and mitigation in analog in-memory computing

DOI: 10.1088/1674-4926/26060006

CSTR: 32376.14.1674-4926.26060006

1.
School of Integrated Circuits, Southeast University, Nanjing 210096, China
2.
Dept. of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, Hong Kong 999077, China

More Information

Zeying Ding received the B.S. degree from Jilin University, Changchun, China, in 2021, and the M.E. degree from the University of Chinese Academy of Sciences, Beijing, China, in 2024. She is currently pursuing the Ph.D. degree with the School of Integrated Circuits, Southeast University, Nanjing, China. Her research interests include magnetic random-access memory circuit design, MRAM-based in-memory computing, and neuromorphic computing circuits
Yantong Di received the B.Eng. degree in electronic science and technology from Southeast University, Nanjing, China, in 2022, and the M.Sc. degree in IC design engineering from The Hong Kong University of Science and Technology, Hong Kong, China, in 2024. She is currently pursuing the Ph.D. degree with the School of Integrated Circuits, Southeast University, Nanjing, China. Her research interests include MRAM device modeling and design-technology co-optimization, radiation-hardened circuit design, and MRAM-based computing
Haoran Du received the B.S. degree in physics from University of Washington, Seattle, USA in 2021, and M.S. degree in microelectronics from Newcastle University, Newcastle upon Tyne, U.K. in 2022. He is currently pursuing the Ph.D. degree in integrated circuit engineering with Southeast University, Nanjing, China. His research interests include circuit design of MRAM design, non-volatile computing in memory, and design-technology co-optimization
Haoran Chen received the B.Eng. degree from Shandong University, Weihai, China, in 2025. He is currently pursuing the M.Eng. degree at Southeast University. His research interests include computer architecture and memory systems
Yaoru Hou received the B.S. and M.S. degrees from Southeast University, Nanjing, China, in 2016 and 2023, respectively. He is currently pursuing the Ph.D. degree in Electronic and Computer Engineering at the Hong Kong University of Science and Technology. His research interests include MTJ device modeling, MRAM circuit design, and spintronic-based unconventional AI accelerators. He has authored or co-authored five papers in major international conferences, including IEDM, ISSCC, and CICC. He has participated in five chip tape-outs involving CMOS-integrated STT-, SOT-, and VCMA-MTJ technologies targeting MRAM commercialization
Bo Liu received the B.S. and Ph.D. degrees in electronic science and engineering from Southeast University, Nanjing, China, in 2006 and 2013, respectively. He is currently an Associate Professor with the National ASIC System Engineering Research Center, School of Integrated Circuits, Southeast University. His research is supported by the National Natural Science Foundation, the National Science and Technology Major Project, and the National Key Research and Development Program. He has authored or co-authored three book chapters and more than 60 scientific papers, including Nature Electronics, MICRO, ISSCC, DAC, TCAS-I,TCAS-II, TCAD, and IEEE Circuits and Systems Magazine. He holds one U.S. patent and more than 30 Chinese patents. His research interests include chip architecture design, reconfigurable computing, and approximate computing
Hao Cai received the master’s degree in electrical engineering from Lund University, Sweden, in 2009, and the Ph.D. degree in electrical engineering from Télécom ParisTech, France, in 2013. From 2013 to 2017, he was with Université Paris-Saclay, France, working on reliable low-power integrated circuit design. In 2018, he joined the National ASIC System Engineering Center, Southeast University, Nanjing, China, where he is currently a Professor. In 2019, he was with Semiconductor Manufacturing International Corporation (SMIC), working on high-density FinFET MRAM. He is also working on low-power MRAM design and device-circuit design interaction. He has been serving on IEEE-CAS technical committees and as a conference TPC member for DAC, GLSVLSI, Nanoarch, ESREF, and NEWCAS. He has authored or co-authored over 120 scientific articles and received several conference best paper awards
Corresponding author: hao.cai@seu.edu.cn; yhouas@connect.ust.hk
Received Date: 2026-06-02
Revised Date: 2026-08-01

Available Online: 2026-09-10

Abstract

Abstract

Analog in-memory computing (AIMC) has attracted significant attention as an energy-efficient computing paradigm for data-intensive workloads. However, its practical deployment is fundamentally limited by various non-idealities across multiple abstraction levels, which degrade computational accuracy and reliability. This paper presents a comprehensive review of non-idealities in AIMC systems from a cross-layer perspective. A common computational representation is introduced to illustrate how diverse physical non-idealities may manifest as weight perturbations, multiplicative distortions, nonlinear transfer effects, additive errors, and quantization or accumulation errors. From this perspective, we review design techniques across device, array, circuit, data-conversion, and system levels, and discuss how errors are generated, transformed, and accumulated throughout the computation flow. Furthermore, algorithm-hardware co-design strategies are discussed as an effective approach to mitigate cross-layer errors and enhance system robustness. By providing a structured overview of error generation, transformation, and propagation, this work highlights the importance of cross-layer co-design and offers insights into the design trade-offs among accuracy, efficiency, and scalability in AIMC systems.
- analog in-memory computing (AIMC),
- cross-layer perspective,
- non-idealities,
- error propagation,
- algorithm-hardware co-design

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