Design and measurement of a 53 GHz balanced Colpitts oscillator

Zhao Yan; Wang Zhigong; Li Wei; Zhang Li

doi:10.1088/1674-4926/30/1/015003

J. Semicond. > 2009, Volume 30 > Issue 1 > 015003

SEMICONDUCTOR INTEGRATED CIRCUITS

Design and measurement of a 53 GHz balanced Colpitts oscillator

Zhao Yan, Wang Zhigong, Li Wei and Zhang Li

+ Author Affiliations

DOI: 10.1088/1674-4926/30/1/015003

Abstract: A 53 GHz Colpitts oscillator implemented in a SiGe:C BiCMOS technology is presented. Limited by a 26.5 GHz frequency analyzer, the oscillator was measured indirectly through an on-chip mixer. The mixer down-converted the oscillating frequency to an intermediate frequency (IF) below 26.5 GHz. By adjusting the local oscillating (LO) frequency and recording the changes of IF frequency, the oscillator's output frequency (RF) was determined. Additionally, using phase noise theory of mixers, the oscillator's phase noise was estimated as -58 dBc/Hz at 1 MHz offset and the output power was about -21 dBm. The chip is 270×480 μm² in size.

Key words: Colpitts, negative resistance, oscillator, phase noise

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Received: 18 August 2015 Revised: Online: Published: 01 January 2009

A 53 GHz Colpitts oscillator implemented in a SiGe:C BiCMOS technology is presented. Limited by a 26.5 GHz frequency analyzer, the oscillator was measured indirectly through an on-chip mixer. The mixer down-converted the oscillating frequency to an intermediate frequency (IF) below 26.5 GHz. By adjusting the local oscillating (LO) frequency and recording the changes of IF frequency, the oscillator's output frequency (RF) was determined. Additionally, using phase noise theory of mixers, the oscillator's phase noise was estimated as -58 dBc/Hz at 1 MHz offset and the output power was about -21 dBm. The chip is 270×480 μm² in size.

Design and measurement of a 53 GHz balanced Colpitts oscillator

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