A 10–20 Gb/s PAM2-4 transceiver in 65 nm CMOS

Gao Zhuo; Yang Yi; Zhong Shiqiang; Yang Xu; Huang Lingyi; Hu Weiwu

doi:10.1088/1674-4926/30/1/015004

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Article Navigation > Journal of Semiconductors > 2009 > 30(1): 015004

Gao Zhuo, Yang Yi, Zhong Shiqiang, Yang Xu, Huang Lingyi, Hu Weiwu. A 10–20 Gb/s PAM2-4 transceiver in 65 nm CMOS[J]. Journal of Semiconductors, 2009, 30(1): 015004. doi: 10.1088/1674-4926/30/1/015004 ****Gao Z, Yang Y, Zhong S Q, Yang X, Huang L Y, Hu W W. A 10–20 Gb/s PAM2-4 transceiver in 65 nm CMOS[J]. J. Semicond., 2009, 30(1): 015004. doi: 10.1088/1674-4926/30/1/015004.

Citation:

Gao Zhuo, Yang Yi, Zhong Shiqiang, Yang Xu, Huang Lingyi, Hu Weiwu. A 10–20 Gb/s PAM2-4 transceiver in 65 nm CMOS[J]. Journal of Semiconductors, 2009, 30(1): 015004. doi: 10.1088/1674-4926/30/1/015004 ****

Gao Z, Yang Y, Zhong S Q, Yang X, Huang L Y, Hu W W. A 10–20 Gb/s PAM2-4 transceiver in 65 nm CMOS[J]. J. Semicond., 2009, 30(1): 015004. doi: 10.1088/1674-4926/30/1/015004.

Citation:

Gao Z, Yang Y, Zhong S Q, Yang X, Huang L Y, Hu W W. A 10–20 Gb/s PAM2-4 transceiver in 65 nm CMOS[J]. J. Semicond., 2009, 30(1): 015004. doi: 10.1088/1674-4926/30/1/015004.

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A 10–20 Gb/s PAM2-4 transceiver in 65 nm CMOS

DOI: 10.1088/1674-4926/30/1/015004

Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China
Graduate University of the Chinese Academy of Sciences, Beijing 100049, China
Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China
Graduate University of the Chinese Academy of Sciences, Beijing 100049, China
Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China
Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190,
Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China
Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China

Received Date: 2015-08-18

Abstract

Abstract

This paper presents the design of a 10 Gb/s PAM2, 20 Gb/s PAM4 high speed low power wire-line transceiver equalizer in a 65 nm CMOS process with 1 V supply voltage. The transmitter occupies 430 × 240 μm2 and consumes 50.56 mW power. With the programmable 5-order pre-emphasis equalizer, the transmitter can compensate for a wide range of channel loss and send a signal with adjustable voltage swing. The receiver equalizer occupies 146 × 186 μm2 and consumes 5.3 mW power.
- serial link,
- PAM,
- equalizer,
- pre-emphasis,
- CTLE

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A 10–20 Gb/s PAM2-4 transceiver in 65 nm CMOS

DOI: 10.1088/1674-4926/30/1/015004

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A 10–20 Gb/s PAM2-4 transceiver in 65 nm CMOS

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