5-Gb/s 0.18-<i>µ</i>m CMOS 2 : 1 multiplexer with integrated clock extraction

Zhang Changchun; Wang Zhigong; Shi Si; Miao Peng; Tian Ling

doi:10.1088/1674-4926/30/9/095009

J. Semicond. > 2009, Volume 30 > Issue 9 > 095009

SEMICONDUCTOR INTEGRATED CIRCUITS

5-Gb/s 0.18-µm CMOS 2 : 1 multiplexer with integrated clock extraction

Zhang Changchun, Wang Zhigong, Shi Si, Miao Peng and Tian Ling

+ Author Affiliations

DOI: 10.1088/1674-4926/30/9/095009

Abstract:

A 5-Gb/s 2 : 1 MUX (multiplexer) with an on-chip integrated clock extraction circuit which possesses the function of automatic phase alignment (APA), has been designed and fabricated in SMIC's 0.18 μm CMOS technology. The chip area is 670 × 780 μm2 . At a single supply voltage of 1.8 V, the total power consumption is 112 mW with an input sensitivity of less than 50 mV and an output single-ended swing of above 300 mV. The measurement results show that the IC can work reliably at any input data rate between 1.8 and 2.6 Gb/s with no need for external components, reference clock, or phase alignment between data and clock. It can be used in a parallel optic-fiber data interconnecting system.

Key words: multiplexer, clock extraction, automatic phase alignment, phase frequency detector, voltage-controlled oscillator

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Zhang Changchun, Wang Zhigong, Shi Si, Miao Peng, Tian Ling. 5-Gb/s 0.18-µm CMOS 2 : 1 multiplexer with integrated clock extraction[J]. Journal of Semiconductors, 2009, 30(9): 095009. doi: 10.1088/1674-4926/30/9/095009

Zhang C C, Wang Z G, Shi S, Miao P, Tian L. 5-Gb/s 0.18-m CMOS 2 : 1 multiplexer with integrated clock extraction[J]. J. Semicond., 2009, 30(9): 095009. doi: 10.1088/1674-4926/30/9/095009.