Security strategy of powered-off SRAM for resisting physical attack to data remanence

Yu Kai; Zou Xuecheng; Yu Guoyi; Wang Weixu

doi:10.1088/1674-4926/30/9/095010

J. Semicond. > 2009, Volume 30 > Issue 9 > 095010

SEMICONDUCTOR INTEGRATED CIRCUITS

Security strategy of powered-off SRAM for resisting physical attack to data remanence

Yu Kai, Zou Xuecheng, Yu Guoyi and Wang Weixu

+ Author Affiliations

DOI: 10.1088/1674-4926/30/9/095010

Abstract: This paper presents a security strategy for resisting a physical attack utilizing data remanence in powered-off static random access memory (SRAM). Based on the mechanism of physical attack to data remanence, the strategy intends to erase data remanence in memory cells once the power supply is removed, which disturbs attackers trying to steal the right information. Novel on-chip secure circuits including secure power supply and erase transistor are integrated into conventional SRAM to realize erase operation. Implemented in 0.25 μm Huahong-NEC CMOS technology, an SRAM exploiting the proposed security strategy shows the erase operation is accomplished within 0.2 μs and data remanence is successfully eliminated. Compared with conventional SRAM, the retentive time of data remanence is reduced by 82% while the operation power consumption only increases by 7%.

Key words: SRAM

1	6T SRAM cell analysis for DRV and read stability Ruchi, S.Dasgupta Journal of Semiconductors, 2017, 38(2): 025001. doi: 10.1088/1674-4926/38/2/025001
2	Memristive SRAM cell of seven transistors and one memristor Patrick W. C. Ho, Haider Abbas F. Almurib, T. Nandha Kumar Journal of Semiconductors, 2016, 37(10): 104002. doi: 10.1088/1674-4926/37/10/104002
3	Monolithically integrated enhancement/depletion-mode AlGaN/GaN HEMTsSRAM unit and voltage level shifter using fluorine plasma treatment Yonghe Chen, Xuefeng Zheng, Jincheng Zhang, Xiaohua Ma, Yue Hao, et al. Journal of Semiconductors, 2016, 37(5): 055002. doi: 10.1088/1674-4926/37/5/055002
4	Simulation and research on a 4T-cell based duplication redundancy SRAM for SEU radiation hardening Xinhong Hong, Liyang Pan, Wendi Zhang, Dongmei Ji, Dong Wu, et al. Journal of Semiconductors, 2015, 36(11): 114003. doi: 10.1088/1674-4926/36/11/114003
5	SRAM standby leakage decoupling analysis for different leakage reduction techniques Qing Dong, Yinyin Lin Journal of Semiconductors, 2013, 34(4): 045008. doi: 10.1088/1674-4926/34/4/045008
6	Total dose ionizing irradiation effects on a static random access memory field programmable gate array Gao Bo, Yu Xuefeng, Ren Diyuan, Li Yudong, Sun Jing, et al. Journal of Semiconductors, 2012, 33(3): 034007. doi: 10.1088/1674-4926/33/3/034007
7	A 200 mV low leakage current subthreshold SRAM bitcell in a 130 nm CMOS process Bai Na, Lü Baitao Journal of Semiconductors, 2012, 33(6): 065008. doi: 10.1088/1674-4926/33/6/065008
8	Worst-case total dose radiation effect in deep-submicron SRAM circuits Ding Lili, Yao Zhibin, Guo Hongxia, Chen Wei, Fan Ruyu, et al. Journal of Semiconductors, 2012, 33(7): 075010. doi: 10.1088/1674-4926/33/7/075010
9	An IO block array in a radiation-hardened SOI SRAM-based FPGA Zhao Yan, Wu Lihua, Han Xiaowei, Li Yan, Zhang Qianli, et al. Journal of Semiconductors, 2012, 33(1): 015010. doi: 10.1088/1674-4926/33/1/015010
10	Gate leakage current reduction in IP3 SRAM cells at 45 nm CMOS technology for multimedia applications R. K. Singh, Neeraj Kr. Shukla, Manisha Pattanaik Journal of Semiconductors, 2012, 33(5): 055001. doi: 10.1088/1674-4926/33/5/055001
11	Analysis and optimization of current sensing circuit for deep sub-micron SRAM Wang Yiqi, Zhao Fazhan, Liu Mengxin, Lü Yinxue, Zhao Bohua, et al. Journal of Semiconductors, 2011, 32(11): 115016. doi: 10.1088/1674-4926/32/11/115016
12	Novel SEU hardened PD SOI SRAM cell Xie Chengmin, Wang Zhongfang, Wang Xihu, Wu Longsheng, Liu Youbao, et al. Journal of Semiconductors, 2011, 32(11): 115017. doi: 10.1088/1674-4926/32/11/115017
13	A novel high reliability CMOS SRAM cell Xie Chengmin, Wang Zhongfang, Wu Longsheng, Liu Youbao Journal of Semiconductors, 2011, 32(7): 075011. doi: 10.1088/1674-4926/32/7/075011
14	An ultra-low-power 1 kb sub-threshold SRAM in the 180 nm CMOS process Liu Ming, Chen Hong, Li Changmeng, Wang Zhihua Journal of Semiconductors, 2010, 31(6): 065013. doi: 10.1088/1674-4926/31/6/065013
15	Optimization and Application of SRAM in 90nm CMOS Technology Zhou Qingjun, Liu Hongxia Journal of Semiconductors, 2008, 29(5): 883-888.
16	Design of a High-Speed Low-Power 9-Port Register File Cong Gaojian, Qi Jiayue Chinese Journal of Semiconductors , 2007, 28(4): 614-618.
17	Reducing Leakage of SRAM Using Dual-Gate-Oxide-Thickness Transistors in 45nm Bulk Technology Yang Song, Wang Hong, Yang Zhijia Chinese Journal of Semiconductors , 2007, 28(5): 745-749.
18	Circuit Simulation of SEU for SRAM Cells Liu Zheng, Sun Yongjie, Li Shaoqing, Liang Bin Chinese Journal of Semiconductors , 2007, 28(1): 138-141.
19	A Low Power SRAM/SOI Memory Cell Design Yu Yang, Zhao Qian, Shao Zhibiao Chinese Journal of Semiconductors , 2006, 27(2): 318-322.
20	一种用于SRAM快速仿真的模型 Chinese Journal of Semiconductors , 2005, 26(6): 1264-1268.

Search

GET CITATION

shu

Export: BibTex EndNote

Article Metrics

Article views: 3993 Times PDF downloads: 2645 Times Cited by: 0 Times

History

Received: 18 August 2015 Revised: 07 April 2009 Online: Published: 01 September 2009

This paper presents a security strategy for resisting a physical attack utilizing data remanence in powered-off static random access memory (SRAM). Based on the mechanism of physical attack to data remanence, the strategy intends to erase data remanence in memory cells once the power supply is removed, which disturbs attackers trying to steal the right information. Novel on-chip secure circuits including secure power supply and erase transistor are integrated into conventional SRAM to realize erase operation. Implemented in 0.25 μm Huahong-NEC CMOS technology, an SRAM exploiting the proposed security strategy shows the erase operation is accomplished within 0.2 μs and data remanence is successfully eliminated. Compared with conventional SRAM, the retentive time of data remanence is reduced by 82% while the operation power consumption only increases by 7%.

Security strategy of powered-off SRAM for resisting physical attack to data remanence

Search

GET CITATION

Share:

Article Metrics

History

Catalog

Email This Article

Security strategy of powered-off SRAM for resisting physical attack to data remanence

DOI: 10.1088/1674-4926/30/9/095010

Abstract

References

Proportional views

Catalog

Security strategy of powered-off SRAM for resisting physical attack to data remanence

Search

GET CITATION

Share:

Article Metrics

History

Catalog

Email This Article

Security strategy of powered-off SRAM for resisting physical attack to data remanence

DOI: 10.1088/1674-4926/30/9/095010

Abstract

References

Proportional views

Catalog

Export File

Citation

Format

Content