| Citation: |
Zhang Zhenlong, Liu Xiangyang, Mao Yanli. Design and fabrication of a planar patch-clamp substrate using a silicon-on-insulator wafer[J]. Journal of Semiconductors, 2009, 30(9): 096001. doi: 10.1088/1674-4926/30/9/096001
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Zhang Z L, Liu X Y, Mao Y L. Design and fabrication of a planar patch-clamp substrate using a silicon-on-insulator wafer[J]. J. Semicond., 2009, 30(9): 096001. doi: 10.1088/1674-4926/30/9/096001.
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Design and fabrication of a planar patch-clamp substrate using a silicon-on-insulator wafer
DOI: 10.1088/1674-4926/30/9/096001
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Abstract
The planar patch-clamp technique has been applied to high throughput screening in drug discovery. The key feature of this technique is the fabrication of a planar patch-clamp substrate using appropriate materials. In this study, a planar patch-clamp substrate was designed and fabricated using a silicon-on-insulator (SOI) wafer. The access resistance and capacitance of SOI-based planar patch-clamp substrates are smaller than those of bulk silicon-based planar substrates, which will reduce the distributed RC noise. -
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