SEMICONDUCTOR INTEGRATED CIRCUITS
Lin Li, Ren Junyan and Ye Fan
Abstract: A 600-MSample/s 6-bit folding and interpolating analog-to-digital converter (ADC) is presented. This ADC with single track-and-hold (T/H) circuits is based on cascaded folding amplifiers and input-connection-improved active interpolating amplifiers. The prototype ADC achieves 5.55 bits of the effective number of bits (ENOB) and 47.84 dB of the spurious free dynamic range (SFDR) at 10-MHz input and 4.3 bit of ENOB and 35.65 dB of SFDR at 200-MHz input with a 500 MS/s sampling rate; it achieves 5.48 bit of ENOB and 43.52 dB of SFDR at 1-MHz input and 4.66 bit of ENOB and 39.56 dB of SFDR at 30.1-MHz input with a 600-MS/s sampling rate. This ADC has a total power consumption of 25 mW from a 1.4 V supply voltage and occupies 0.17 mm2 in the 0.13-μm CMOS process.
Key words: analog-to-digital converter, cascaded folding, active interpolating
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Received: 18 August 2015 Revised: 10 September 2009 Online: Published: 01 February 2010
| Citation: |
Lin Li, Ren Junyan, Ye Fan. A 1.4-V 25-mW 600-MS/s 6-bit folding and interpolating ADC in 0.13-μm CMOS[J]. Journal of Semiconductors, 2010, 31(2): 025009. doi: 10.1088/1674-4926/31/2/025009
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Lin L, Ren J Y, Ye F. A 1.4-V 25-mW 600-MS/s 6-bit folding and interpolating ADC in 0.13-μm CMOS[J]. J. Semicond., 2010, 31(2): 025009. doi: 10.1088/1674-4926/31/2/025009.
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