| Citation: |
Xu Bulu, Shao Bowen, Lin Xia, Yi Wei, Liu Yun. Design and verification of a 10-bit 1.2-V 100-MSPS D/A IP core based on a 0.13-μm low power CMOS process[J]. Journal of Semiconductors, 2010, 31(9): 095007. doi: 10.1088/1674-4926/31/9/095007
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Xu B L, Shao B W, Lin X, Yi W, Liu Y. Design and verification of a 10-bit 1.2-V 100-MSPS D/A IP core based on a 0.13-μm low power CMOS process[J]. J. Semicond., 2010, 31(9): 095007. doi: 10.1088/1674-4926/31/9/095007.
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Design and verification of a 10-bit 1.2-V 100-MSPS D/A IP core based on a 0.13-μm low power CMOS process
doi: 10.1088/1674-4926/31/9/095007
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Abstract
Based on a low supply voltage curvature-compensated bandgap reference and central symmetry Q2 random walk NMOS current source layout routing method, a 1.2-V 10-bit 100-MSPS CMOS current-steering digital-to-analog converter is implemented in a SMIC 0.13-μm CMOS process. The total consumption is only 10 mW from a single 1.2-V power supply, and the integral and differential nonlinearity are measured to be less than 1 LSB and 0.5 LSB, respectively. When the output signal frequency is 1–5 MHz at 100-MSPS sampling rate, the SFDR is measured to be 70 dB. The die area is about 0.2 mm2. -
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