| Citation: |
Fan Hua, Wei Qi, Kobenge Sekedi Bomeh, Yin Xiumei, Yang Huazhong. An 8-bit 180-kS/s differential SAR ADC with a time-domain comparator and 7.97-ENOB[J]. Journal of Semiconductors, 2010, 31(9): 095011. doi: 10.1088/1674-4926/31/9/095011
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Fan H, Wei Q, Kobenge S B, Yin X M, Yang H Z. An 8-bit 180-kS/s differential SAR ADC with a time-domain comparator and 7.97-ENOB[J]. J. Semicond., 2010, 31(9): 095011. doi: 10.1088/1674-4926/31/9/095011.
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An 8-bit 180-kS/s differential SAR ADC with a time-domain comparator and 7.97-ENOB
doi: 10.1088/1674-4926/31/9/095011
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Abstract
This paper presents a differential successive approximation register analog-to-digital converter (SAR ADC) with a novel time-domain comparator design for wireless sensor networks. The prototype chip has been implemented in the UMC 0.18-μm 1P6M CMOS process. The proposed ADC achieves a peak ENOB of 7.98 at an input frequency of 39.7 kHz and sampling rate of 180 kHz. With the Nyquist input frequency, 68.49-dB SFDR, 7.97-ENOB is achieved. A simple quadrate layout is adopted to ease the routing complexity of the common-centroid symmetry layout. The ADC maintains a maximum differential nonlinearity of less than 0.08 LSB and integral nonlinearity less than 0.34 LSB by this type of layout. -
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