| Citation: |
Chu Xiaojie, Jia Hailong, Lin Min, Shi Yin, Dai Fa Foster. A 0.13 μm CMOS ΔΣ fractional-N frequency synthesizer for WLAN transceivers[J]. Journal of Semiconductors, 2011, 32(10): 105006. doi: 10.1088/1674-4926/32/10/105006
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Chu X J, Jia H L, Lin M, Shi Y, Dai F F. A 0.13 μm CMOS ΔΣ fractional-N frequency synthesizer for WLAN transceivers[J]. J. Semicond., 2011, 32(10): 105006. doi: 10.1088/1674-4926/32/10/105006.
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A 0.13 μm CMOS ΔΣ fractional-N frequency synthesizer for WLAN transceivers
DOI: 10.1088/1674-4926/32/10/105006
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Abstract
A fractional-N frequency synthesizer fabricated in a 0.13 μm CMOS technology is presented for the application of IEEE 802.11 b/g wireless local area network (WLAN) transceivers. A monolithic LC voltage controlled oscillator (VCO) is implemented with an on-chip symmetric inductor. The fractional-N frequency divider consists of a pulse swallow frequency divider and a 3rd-order multistage noise shaping (MASH) ΔΣ modulator with noise-shaped dithering techniques. Measurement results show that in all channels, phase noise of the synthesizer achieves -93 dBc/Hz and -118 dBc/Hz in band and out of band respectively with a phase-frequency detector (PFD) frequency of 20 MHz and a loop bandwidth of 100 kHz. The integrated RMS phase error is no more than 0.8°. The proposed synthesizer consumes 8.4 mW from a 1.2 V supply and occupies an area of 0.86 mm2. -
References
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