| Citation: |
Yuan Jun, Zhang Zhaofeng, Wu Jun, Wang Chao, Chen Zhenhai, Qian Wenrong, Yang Yintang. Continuous time sigma delta ADC design and non-idealities analysis[J]. Journal of Semiconductors, 2011, 32(12): 125007. doi: 10.1088/1674-4926/32/12/125007
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Yuan J, Zhang Z F, Wu J, Wang C, Chen Z H, Qian W R, Yang Y T. Continuous time sigma delta ADC design and non-idealities analysis[J]. J. Semicond., 2011, 32(12): 125007. doi: 10.1088/1674-4926/32/12/125007.
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Continuous time sigma delta ADC design and non-idealities analysis
doi: 10.1088/1674-4926/32/12/125007
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Abstract
A wide bandwidth continuous time sigma delta ADC is implemented in 130 nm CMOS. A detailed non-idealities analysis (excess loop delay, clock jitter, finite gain and GBW, comparator offset and DAC mismatch) is performed developed in Matlab/Simulink. This design is targeted for wide bandwidth applications such as video or wireless base-stations. A third-order continuous time sigma delta modulator comprises a third-order RC operational-amplifier-based loop filter and 3-bit internal quantizer operated at 512 MHz clock frequency. The sigma delta ADC achieves 60 dB SNR and 59.3 dB SNDR over a 16-MHz signal band at an OSR of 16. The power consumption of the CT sigma delta modulator is 22 mW from the 1.2-V supply.-
Keywords:
- ADC
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References
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