Citation: |
Lei Xuemei, Wang Zhigong, Wang Keping. A wideband low power low phase noise dual-modulus prescaler[J]. Journal of Semiconductors, 2011, 32(2): 025011. doi: 10.1088/1674-4926/32/2/025011
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Lei X M, Wang Z G, Wang K P. A wideband low power low phase noise dual-modulus prescaler[J]. J. Semicond., 2011, 32(2): 025011. doi: 10.1088/1674-4926/32/2/025011.
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Abstract
This paper describes a novel divide-by-32/33 dual-modulus prescaler (DMP). Here, a new combination of DFF has been introduced in the DMP. By means of the cooperation and coordination among three types, DFF, SCL, TPSC, and CMOS static flip-flop, the DMP demonstrates high speed, wideband, and low power consumption with low phase noise. The chip has been fabricated in a 0.18-μm CMOS process of SMIC. The measured results show that the DMP's operating frequency is from 0.9 to 3.4 GHz with a maximum power consumption of 2.51 mW under a 1.8 V power supply and the phase noise is --134.78 dBc/Hz at 1 MHz offset from the 3.4 GHz carrier. The core area of the die without PAD is 57 × 30 μm2. Due to its excellent performance, the DMP could be applied to a PLL-based frequency synthesizer for many RF systems, especially for multi-standard radio applications.-
Keywords:
- dual-modulus prescaler
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References
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