| Citation: |
Su Yongbo, Jin Zhi, Cheng Wei, Ge Ji, Wang Xiantai, Chen Gaopeng, Liu Xinyu, Xu Anhuai, Qi Ming. An InGaAs/InP 40 GHz CML static frequency divider[J]. Journal of Semiconductors, 2011, 32(3): 035008. doi: 10.1088/1674-4926/32/3/035008
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Su Y B, Jin Z, Cheng W, Ge J, Wang X T, Chen G P, Liu X Y, Xu A H, Qi M. An InGaAs/InP 40 GHz CML static frequency divider[J]. J. Semicond., 2011, 32(3): 035008. doi: 10.1088/1674-4926/32/3/035008.
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Abstract
Static frequency dividers are widely used as a circuit performance benchmark or figure-of-merit indicator to gauge a particular device technology's ability to implement high speed digital and integrated high performance mixed-signal circuits. We report a 2 : 1 static frequency divider in InGaAs/InP heterojunction bipolar transistor technology. This is the first InP based digital integrated circuit ever reported on the mainland of China. The divider is implemented in differential current mode logic (CML) with 30 transistors. The circuit operated at a peak clock frequency of 40 GHz and dissipated 650 mW from a single –5 V supply.-
Keywords:
- InP,
- DHBT,
- static frequency divider
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References
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Proportional views
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