A programmable gain amplifier with a DC offset calibration loop for a direct-conversion WLAN transceiver

Lei Qianqian; Lin Min; Chen Zhiming; Shi Yin

doi:10.1088/1674-4926/32/4/045006

J. Semicond. > 2011, Volume 32 > Issue 4 > 045006

SEMICONDUCTOR INTEGRATED CIRCUITS

A programmable gain amplifier with a DC offset calibration loop for a direct-conversion WLAN transceiver

Lei Qianqian, Lin Min, Chen Zhiming and Shi Yin

+ Author Affiliations

DOI: 10.1088/1674-4926/32/4/045006

Abstract: A high-linearity PGA (programmable gain amplifier) with a DC offset calibration loop is proposed. The PGA adopts a differential degeneration structure to vary voltage gain and uses the closed-loop structure including the input op-amps to enhance the linearity. A continuous time feedback based DC offset calibration loop is also designed to solve the DC offset problem. This PGA is fabricated by TSMC 0.13 μm CMOS technology. The measurements show that the receiver PGA (RXPGA) provides a 64 dB gain range with a step of 1 dB, and the transmitter PGA (TXPGA) covers a 16 dB gain. The RXPGA consumes 18 mA and the TXPGA consumes 7 mA (I and Q path) under a 3.3 V supply. The bandwidth of the multi-stage PGA is higher than 20 MHz. In addition, the DCOC (DC offset cancellation) circuit shows 10 kHz of HPCF (high pass cutoff frequency) and the DCOC settling time is less than 0.45 μs.

Key words: linear-in-dB, PGA, DC offset calibration

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Received: 18 August 2015 Revised: 24 October 2010 Online: Published: 01 April 2011

A high-linearity PGA (programmable gain amplifier) with a DC offset calibration loop is proposed. The PGA adopts a differential degeneration structure to vary voltage gain and uses the closed-loop structure including the input op-amps to enhance the linearity. A continuous time feedback based DC offset calibration loop is also designed to solve the DC offset problem. This PGA is fabricated by TSMC 0.13 μm CMOS technology. The measurements show that the receiver PGA (RXPGA) provides a 64 dB gain range with a step of 1 dB, and the transmitter PGA (TXPGA) covers a 16 dB gain. The RXPGA consumes 18 mA and the TXPGA consumes 7 mA (I and Q path) under a 3.3 V supply. The bandwidth of the multi-stage PGA is higher than 20 MHz. In addition, the DCOC (DC offset cancellation) circuit shows 10 kHz of HPCF (high pass cutoff frequency) and the DCOC settling time is less than 0.45 μs.

A programmable gain amplifier with a DC offset calibration loop for a direct-conversion WLAN transceiver

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A programmable gain amplifier with a DC offset calibration loop for a direct-conversion WLAN transceiver

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A programmable gain amplifier with a DC offset calibration loop for a direct-conversion WLAN transceiver

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