SEMICONDUCTOR INTEGRATED CIRCUITS
Abstract: A 1.2 GHz frequency synthesizer integrated in a RF receiver for Beidou navigation is implemented in standard 0.18 μ m CMOS technology. A distributed biased varactor LC voltage-controlled oscillator is employed to achieve low tuning sensitivity and optimized phase noise performance. A high-speed and low-switching-noise divider-by-2 circuit based on a source-coupled logic structure is adopted to generate a quadrature (I/Q) local oscillating signal. A high-speed 8/9 dual-modulus prescaler (DMP), a programmable-delay phase frequency detector without dead-zone problem, and a programmable-current charge pump are also integrated into the frequency synthesizer. The frequency synthesizer demonstrates an output frequency from 1.05 to 1.30 GHz, and the phase noise is –98.53 dBc/Hz at 100-kHz offset and –121.92 dBc/Hz at 1-MHz offset from the carrier frequency of 1.21 GHz. The power dissipation of the core circuits without the output buffer is 9.8 mW from a 1.8 V power supply. The total area of the receiver is 2.4 × 1.6 mm2.
Key words: Beidou receiver, frequency synthesizer, voltage-controlled oscillator, quadrature output divider, phase noise
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Received: 18 August 2015 Revised: 20 March 2011 Online: Published: 01 July 2011
| Citation: |
Li Zhenrong, Zhuang Yiqi, Li Bing, Jin Gang. A 9.8-mW 1.2-GHz CMOS frequency synthesizer with a low phase-noise LC-VCO and an I/Q frequency divider[J]. Journal of Semiconductors, 2011, 32(7): 075008. doi: 10.1088/1674-4926/32/7/075008
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Li Z R, Zhuang Y Q, Li B, Jin G. A 9.8-mW 1.2-GHz CMOS frequency synthesizer with a low phase-noise LC-VCO and an I/Q frequency divider[J]. J. Semicond., 2011, 32(7): 075008. doi: 10.1088/1674-4926/32/7/075008.
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