
SEMICONDUCTOR INTEGRATED CIRCUITS
Chen Liang and Li Zhiqun
Abstract: This paper presents a low noise amplifier (LNA), which could work at an ultra-low voltage of 0.5 V and was optimized for WSN application using 0.13 μm RF-CMOS technology. The circuit was analyzed and a new optimization method for a folded cascode LNA was introduced. Measured results of the proposed circuit demonstrated a power gain of 14.13 dB, consuming 3 mW DC power, showing 1.96 dB NF and an input 1-dB compression point of -19.9 dBm. Both input power matching (S11) and output power matching (S22) were below -10 dB. The results indicate that this LNA is fully applicable to low voltage and low power applications.
Key words: LNA
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Received: 20 August 2015 Revised: 20 April 2012 Online: Published: 01 October 2012
Citation: |
Chen Liang, Li Zhiqun. Design and optimization of a 0.5 V CMOS LNA for 2.4-GHz WSN application[J]. Journal of Semiconductors, 2012, 33(10): 105009. doi: 10.1088/1674-4926/33/10/105009
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Chen L, Li Z Q. Design and optimization of a 0.5 V CMOS LNA for 2.4-GHz WSN application[J]. J. Semicond., 2012, 33(10): 105009. doi: 10.1088/1674-4926/33/10/105009.
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