Abstract: Low-frequency and High-frequency Capacitance-Voltage (C-V) curves of Silicon Metal-Oxide-linebreak Semiconductor Capacitors, showing electron and hole trapping at shallow-level dopant and deep-level generation-recombination-trapping impurities, are presented to illustrate the enhancement of the giant trapping capacitances by physical means via device and circuit designs, in contrast to chemical means via impurity characteristics previously reported. Enhancement is realized by masking the electron or/and hole storage capacitances to make the trapping capacitances dominant at the terminals. Device and materials properties used in the computed CV curves are selected to illustrate experimental realizations for fundamental trapping parameter characterizations and for electrical and optical signal processing applications.

Key words: MOS, silicon, trapping capacitance, dopant impurities, donors, acceptors