Abstract: This paper presents a method of designing a 65 nm DFM standard cell library. By reducing the amount of the library largely, the process of optical proximity correction (OPC) becomes more efficient and the need for large storage is reduced. This library is more manufacture-friendly as each cell has been optimized according to the DFM rule and optical simulation. The area penalty is minor compared with traditional library, and the timing, as well as power has a good performance. Furthermore, this library has passed the test from the Technology Design Department of Foundry. The result shows this DFM standard cell library has advantages that improve the yield.

Key words: design for manufacturability, reduced standard cell library, layout optimization, optical simulation, yield