Abstract: Single event gate rupture (SEGR) is a very important failure mode for power MOSFETs when used in aerospace applications, and the cell regions are widely considered to be the most sensitive to SEGR. However, experimental results show that SEGR can also happen in the gate bus regions. In this paper, we used simulation tools to estimate three structures in power MOSFETs, and found that if certain conditions are met, areas other than cell regions can become sensitive to SEGR. Finally, some proposals are given as to how to reduce SEGR in different regions.

Key words: single event gate rupture