1. Introduction

With the aggressive VLSI technology shrinking, an increasing number of interconnecting wire layers and a greater length of global interconnects are needed to diminish the design complexity, and the number of layers will reach 14 by 2017^[1]. For this reason, the features of global interconnects such as delay, power dissipation and signal integrity are the main factors dominating the performance of a circuit. Consequently the global interconnect has become the center of the chip design flow^[2-5]. Considering the fact that long global interconnects lead to a decline of the interconnect delay and signal integrity, buffer insertion techniques are adopted to reduce the defects of long global interconnects. As a result the number of buffers per chip reaches one billion in the end of the current decade^[6].

In a practical application, the optimal buffer insertion technique gains much attention of researchers because of the wire sizing problem^[2-18]. In Ref. [7] the interconnection wire width optimization method which depends on the wire spacing has been proposed for compromising interconnect power dissipation and delay. An optimal model to minimize interconnect power dissipation and area with constrains of target delay and target bandwidth is present in Ref. [8]. A methodology to include robustness optimization in power-delay optimal buffer insertion is proposed in Ref. [9]. However, these studies do not take into account the self-heating effects. In fact, since the global-tier interconnects are far away from the substrate attached to the heat sink, and the low dielectric constant materials with a low thermal conductivity widely used in VLSI circuit is adverse to the heat transfer, the metal self-heating caused by the flow of the current makes the temperature of global interconnects much higher than the die temperature^{[2, 3]}. Therefore, as the interconnect resistance has a linear relationship with temperature, the self-heating effect greatly affects global interconnect performance and electro migration reliability. For nanometer high-performance circuits, ignoring self-heating effects may incur significant timing violations.

In this paper, a novel interconnect optimization methodology with consideration of the self-heating effect is proposed to systematically optimize the buffer insertion global interconnects. Firstly the expression of interconnection resistance per unit length with the consideration of the self-heating effect is deduced in nano-scales CMOS processes. Then the influences of the self-heating effect on the global interconnection delay, bandwidth and power dissipation are analyzed and an FOM optimization model which is tradeoff between delay, power dissipation and bandwidth is put forward. By solving the differential equations of FOM, the optimal interconnect wire width and spacing are obtained. Finally the proposed optimal model has been verified and compared on 90 nm, 65 nm and 40 nm CMOS technologies.

2. Self-heating effect model

In the current technologies of interconnection design, the heat generated by power dissipation $I^{2}R$ is removed through the substrate which is attached to the heat sink, and then the studies of the interconnect optimal model are always at a constant temperature^[1-17]. The existing process corner files just consider the influences of the process fluctuations and the difference of interconnection on interconnect resistance and capacitance. However, since the interconnects, especially the global interconnects, are far away from the substrate and surrounded by low-k dielectrics with a lower thermal conductivity compared to the silicon dioxide, the heat generated cannot be efficiently removed and therefore causes an increase in interconnect temperature. So the self-heating effect is an inseparable aspect of electrical power distribution and signal transmission^{[19, 20]}.

The temperature rise mainly increases the interconnect wire resistance per unit length, thereby deteriorating the interconnect performance. The wire resistance per unit length is inversely proportional to the interconnect wire width when the interconnect temperature is constant, and the expression is $r_{0}$ $=$ $\rho_0$/($wH)$, where $\rho_0$ is the electrical resistivity of interconnect materials, $w$ and $H$ are the width and thickness of the interconnect wire, respectively. However, when the self-heating effect is considered, the interconnect unit resistance is related not only to the wire width but also to the spacing between any two wires. The new expression of the unit resistance is derived as follows.

The metal temperature $T_{\rm m}$ contains two parts and is given by^[21]

$\begin{equation} \label{eq1} T_{\rm m} =T_{\rm ref} +\Delta T_{\rm self-heating}, \end{equation}$

(1)

where $T_{\rm ref}$ is the reference temperature, and $\Delta T_{\rm self-heating }$is the temperature rise due to the self-heating effect. Here, we assume the thermal condition is, in most cases, steady. Then the temperature rise $\Delta T_{\rm self-heating}$ is given by

$\begin{equation} \label{eq2} \Delta T_{\rm self-heating} =(T_{\rm m} -T_{\rm ref} )=\frac{1}{T}\int_0^T {I^2rr_\theta {\rm d}t=I^2_{\rm rms}rr_\theta }, \end{equation}$

(2)

where $I_{\rm rms}$ is the root mean square current passing through the interconnect wire, $I^{2}_{\rm rms}r$ represents the power dissipation on the interconnects, and $r$ is the resistance per unit length, which has a linear relationship with interconnection temperature and can be written as below

$\begin{equation} \label{eq3} r=\frac{\rho }{w H}[1+\beta T_{\rm m}], \end{equation}$

(3)

where $\rho$ is the electrical resistivity at the reference temperature $T_{\rm ref}$, and $\beta$ is the temperature coefficient of resistance.

The thermal impedance of the per unit interconnection length to the substrate $r_{\theta}$ can be expressed as

$\begin{equation} \label{eq4} r_\theta =\frac{1}{2K_{\rm ox} }\left(\ln \frac{w+s}{w}+\frac{2t_{\rm ox} -s}{w+s}\right), \end{equation}$

(4)

where $t_{\rm ox}$ is the interconnect wire dielectric layer thickness, $s$ is the interconnect wire spacing and $K_{\rm ox}$ is the thermal conductivity of dielectric layers.

Substitute Eqs. (2)-(4) into Eq. (1) the expression of $T_{\rm m}$ can be obtained. Without loss of generality, $T_{\rm m}$ can reach up to 200 $℃$ for global interconnects^[22], and $T_{\rm ref}$ is the ambient temperature. So $T_{\rm ref}$ can be ignored and $T_{\rm m}$ is expressed by

$\begin{align} & {{T}_{\text{m}}}=I_{\text{rms}}^{2}\rho \left( \ln \frac{w+s}{w}+\frac{2{{t}_{\text{ox}}}-s}{w+s} \right) \\ & \ \ \ \ \ \ \times {{\left[ 2wH{{K}_{\text{ox}}}-I_{\text{rms}}^{2}\rho \beta \left( \ln \frac{w+s}{w}+\frac{2{{t}_{\text{ox}}}-s}{w+S} \right) \right]}^{\text{-}1}}. \\ \end{align}$

(5)

Substituting Eq. (5) into Eq. (3), the expression of the interconnect resistance per unit length can be obtained as

$\begin{equation} \label{eq6} r=\frac{2\rho K_{\rm ox} }{2wHK_{\rm ox} -I_{\rm rms}^2 \rho \beta \left(\ln \frac{w+S}{w}+\frac{2t_{\rm ox} -s}{w+s}\right)}. \end{equation}$

(6)

According to Eq. (6), we can figure out the dependence of the interconnection resistance per unit length $r$ on both the interconnect wire width $w$ and the spacing between any tow wire $s$.

The research in this paper is based on copper interconnection. Adopting the interconnect wire processing parameter and electric parameter accurately provided in Table 1, the variation of the normalized unit resistance $r$/$r_{0}$ with the interconnect width and spacing is shown in Fig. 1 for a global interconnection with buffer insertion on 40 nm technology, where $r_{0}$ is obtained at the condition of $w =s =w_{\rm min}$. Obviously, $r$ varies inversely with $w$ and $s$, respectively. Figure 1 also shows that $r$ varies very abruptly with the interconnect wire spacing than with the interconnect wire width. It is because the distribution of metal temperature is depended not only on the interconnect wire width but also on the interconnect wire spacing in Eq. (5). Hence the resistance per unit length affected by the temperature is also dependent on the interconnect wire width and the interconnect wire spacing. So the influence of the interconnect spacing on the interconnection resistance per unit length $r$ can not be neglected.

3. Interconnection delay, power dissipation, bandwidth

Global interconnects with optimal number and size of inserted buffers are shown in Fig. 2, where $L_{\rm chip}$ is the chip width for global interconnects and $L$ is the interconnect length. $w+s$ is the global interconnect pitch. Here we assumed that all the global interconnects have the same wire width and wire spacing, then the number of global interconnects $N$ is equal to $L_{\rm chip}$/($w+s)$.

Assume that the length of a single buffer insertion segment line in a long global interconnect is $h$, and the interconnect capacitance per unit length is $c$. For a minimum size buffer, the input capacitance, output capacitance and output resistance are $c_{0}$, $c_{\rm p}$ and $r_{\rm s}$ respectively. Suppose the buffer size is $k$, then the input capacitance, output capacitance and output resistance is $kc_0$, $kc_{\rm p}$ and $r_{\rm s}$/$k$ respectively.

The Elmore delay distributed model is used to estimate the delay of global interconnects in this paper. So the delay of the line segment $\tau$ is described as^{[16, 17]}

$\begin{equation} \label{eq7} \tau =r_{\rm s} (c_0 +c_{\rm p} )+\frac{r_{\rm s}}{k}ch+rhkc_0 +\frac{1}{2}rch^2. \end{equation}$

(7)

When the buffer size $k$ and the length $h$ satisfy the following equations:

$\begin{equation} \label{eq8} k=k_{\rm opt} =\sqrt {\frac{r_{\rm s} c}{rc_0 }}, \end{equation}$

(8)

$\begin{equation} \label{eq9} h=h_{\rm opt} =\sqrt {\frac{2r_{\rm s} (c_0 +c_{\rm p})}{rc}}, \end{equation}$

(9)

where the interconnection capacitance per unit length $c$ can be written as

$\begin{equation} \label{eq10} c=c_{\rm a} +c_{\rm b} w+\frac{c_{\rm c}}{s}, \end{equation}$

(10)

where $c_{\rm a}$ represents the fringing capacitance, $c_{\rm b}$ represents the parallel plate capacitance to the top and bottom layers of metal and $c_{\rm c}$ represents the coupling capacitance between the neighboring interconnects.

The delay of the line segment is optimal. Therefore the optimal delay per unit length ${(\tau /h)_{{\rm{opt}}}}$ can be obtained from Eqs. (7)-(9) as

$\begin{equation} \label{eq11} \left( {\frac{\tau }{h}} \right)_{\rm opt} =2\sqrt {r_{\rm s} c_0 } \left( {1+\sqrt {\frac{1}{2}\left( {1+\frac{c_{\rm p} }{c_0 }} \right)} } \right)\sqrt {rc} . \end{equation}$

(11)

The total delay $D$ of global interconnects is

$\begin{equation} \label{eq12} D=L\cdot \ln 2\cdot \left( {\frac{\tau }{h}} \right)_{\rm opt} . \end{equation}$

(12)

For a single buffer insertion segment line in a long global interconnect, the power dissipation is composed of switching, short-circuit and leakage power. Suppose the power dissipation per unit length is $P_{\rm repeater}$/$h_{\rm opt}$, so the total power of global interconnects is

$\begin{equation} \label{eq13} \begin{split} P{}& =N L\frac{P_{\rm repeater} }{h_{\rm opt} } \\& =\frac{L_{\rm chip} L}{w+s} \left[{\left( {m_1 +m_3 } \right)\left( {1+\sqrt {\frac{1}{2}\left( {1+\frac{c_{\rm p}}{c_0 }} \right)} } \right)+m_2 \sqrt {\frac{1}{2c_0 \left( {c_0 +c_{\rm p}} \right)}} } \right]c, \\ \end{split} \end{equation}$

(13)

where $m_1 =\alpha fV_{\rm dd}^2$, $m_2 =\frac{3}{2}V_{\rm dd}^2 I_{\rm offn} fw_{\rm nmin}$, $m_3 =2\ln 3V_{\rm dd}^2 I_{\rm short-circuit} fw_{\rm nmin}$, and $\alpha$ is the switching activity factor which can be taken as 0.15, $f$ is the clock frequency, $V_{\rm dd}$ is the power supply voltage, $I_{\rm off}$ is the leakage current of NMOS n-channel, $w_{\rm nmin}$ is the width of the NMOS transistor in a minimum sized inverter. $I_{\rm short-curcuit}$ is the short circuit current per transistor width and the normal value is 65 $\mu$A/$\mu$m.

The global interconnection total delay $D$ and the number of interconnects $N$ decide the interconnect bandwidth. The bandwidth $B$ with the optimal buffer insertion shown in Fig. 2 can be defined as

$\begin{equation} \label{eq14} B=N\frac{1}{D}=\frac{1}{\ln 2\cdot 2\sqrt {r_{\rm s} c_0 } \left( {1+\sqrt {\frac{1}{2}\left( {1+\frac{c_{\rm p} }{c_0 }} \right)} } \right)} \frac{1}{\sqrt {rc} \left( {w+s} \right)}. \end{equation}$

(14)

4. The global interconnection width and spacing optimization model considering the self-heating effect

The aim of global interconnection optimization is to obtain small delay per unit length, low power dissipation of the total global interconnection and large bandwidth. Since parameters $r$ and $c$ are functions of the interconnection width $w$ and spacing $s$ expressed in Eqs. (6) and (10) respectively, from Eqs. (11), (13) and (14), the variation tendency of the delay, power dissipation and bandwidth with the interconnection width $w$ and spacing $s$ can be depicted by plotting.

Based on the parameters in Table 2, the comparison of the normalized interconnection delay considering the self-heating effect to that without considering the self-heating effect is shown in Fig. 3, where $\tau_{0}$ is obtained at the condition of $w =s =w_{\rm min}$. It can be seen from Fig. 3 that the delay decreases with the increase of interconnection wire width and spacing, while the error of the delay becomes greater. Figure 3 also shows that the curved surface of interconnection delay considering the self-heating effect varies much more abruptly with the interconnection wire width and spacing than that of no consideration of the self-heating effect.

Figure 4 shows the comparison of the normalized interconnection bandwidth considering self-heating effect with that without considering the self-heating effect. From Fig. 4, it is obvious that the maximum bandwidth can be obtained at $w =w_{\rm min}$, $s =s_{\rm min}$ without considering the self-heating effect, but in the case of considering the self-heating effect, the maximum bandwidth is obtained at $w =w_{\rm min}$, $s =as_{\rm min}$, where 1 $<$ $a$ $<$ 2. The error of the wire spacing at which the maximum bandwidth is achieved is great, thus is bound to lead to the error of the performance which can not be ignored and further affects the entire integrated circuit design. Therefore the self-heating effect is hard to consider when the performance of interconnection wires is analyzed.

The global interconnection power distribution is inversely proportional to the width and spacing of the interconnection from Fig. 5 which is the same as that of the delay. So low power distribution requires large interconnection width and spacing.

The aim of the global interconnect design is to get a small delay per unit length, low power dissipation and large bandwidth simultaneously. Unfortunately, it can be seen from the above discussion, small delay $\tau$ and low power dissipation $P$ require large interconnection width and spacing, but large bandwidth $B$ requires small interconnection width and spacing. Therefore, a trade-off among the delay, power dissipation and the bandwidth can be used as an FOM model:

$\begin{equation} \label{eq15} {\rm FOM}=\frac{\left( {\tau/h} \right)^i P^j}{B^k}, \end{equation}$

(15)

where $i$, $j$ and $k$ are the weight of the cost functions which can be any positive real numbers. The weights $i$, $j$ and $k$imply which design objective is more highly valued. $i=j =k$ indicates that the delay, power dissipation and bandwidth are valued the same in the global interconnection design, while $i$ > $j=k$ indicates that the delay is more important than the power dissipation and bandwidth. The values of $i$, $j$ and $k$ can be chosen according to the design requirements.

According to Eqs. (6), (11) and (14), both the interconnect wire width $w$ and the spacing between any tow wire $s$ decide the interconnection resistance per unit length $r$ considering the self-heating effect and furthermore affect the interconnection delay and bandwidth. So FOM has the following property:

$\begin{equation} \label{eq16} {\rm FOM}\propto \left( {r(w, s)} \right)^{\frac{i+k}{2}}\left( {c(w, s)} \right)^{\frac{i+k}{2}+j}(w+s)^k, \end{equation}$

(16)

which is a function of interconnection width and spacing. Setting the derivatives of FOM with respect to $w$ and $s$ to be zero, the minimum values by solving the partial differential equations can be obtained, which means the optimal width and spacing is gained.

$\begin{equation} \label{eq17} \begin{cases} \frac{\partial {\rm FOM}}{\partial w}=\left( {\frac{i+k}{2}} \right)\left( {r\left( {w, s} \right)} \right)^{(\frac{i+k}{2}-1)}\left( {c\left( {w, s} \right)} \right)^{\left( {\frac{i+k}{2}+j} \right)}\left( {w+s} \right)^k\frac{\partial r}{\partial w} \\ +\left( {\frac{i+k}{2}+j} \right)\left( {r\left( {w, s} \right)} \right)^{(\frac{i+k}{2})}\left( {c\left( {w, s} \right)} \right)^{\left( {\frac{i+k}{2}+j-1} \right)}\left( {w+s} \right)^k\frac{\partial c}{\partial w} \\ +k\left( {r\left( {w, s} \right)} \right)^{(\frac{i+k}{2})}\left( {c\left( {w, s} \right)} \right)^{\left( {\frac{i+k}{2}+j} \right)}\left( {w+s} \right)^{k-1}=0 \\ \frac{\partial {\rm FOM}}{\partial s}=\left( {\frac{i+k}{2}} \right)\left( {r\left( {w, s} \right)} \right)^{(\frac{i+k}{2}-1)}\left( {c\left( {w, s} \right)} \right)^{\left( {\frac{i+k}{2}+j} \right)}\left( {w+s} \right)^k\frac{\partial r}{\partial s} \\ +\left( {\frac{i+k}{2}+j} \right)\left( {r\left( {w, s} \right)} \right)^{(\frac{i+k}{2})}\left( {c\left( {w, s} \right)} \right)^{\left( {\frac{i+k}{2}+j-1} \right)}\left( {w+s} \right)^k\frac{\partial c}{\partial s} \\ +k\left( {r\left( {w, s} \right)} \right)^{(\frac{i+k}{2})}\left( {c\left( {w, s} \right)} \right)^{\left( {\frac{i+k}{2}+j} \right)}\left( {w+s} \right)^{k-1}=0 \\ \text{where} \\ \frac{\partial r}{\partial w}=\frac{-2\rho K_{\rm ox} \left[{2HK_{\rm ox} +I_{\rm rms}^2 \rho \beta \frac{\left( {2t_{\rm ox} w+s^2} \right)}{\left( {w+s} \right)^2w}} \right]} {\left\{ {2wHK_{\rm ox} -I_{\rm rms}^2 \rho \beta [\ln \frac{w+s}{w}+\frac{2t_{\rm ox}-s^2}{w+s}]} \right\}^2} \\ \frac{\partial c}{\partial w}=c_{\rm b} \\ \frac{\partial r}{\partial s}=\frac{2\rho K_{\rm ox} I_{\rm rms}^2 \rho \beta \frac{\left( {2t_{\rm ox} w+2w+s} \right)}{\left( {w+s} \right)^2}} {\left\{ {2wHK_{\rm ox} -I_{\rm rms}^2 \rho \beta [\ln \frac{w+s}{w}+\frac{2t_{\rm ox}-s^2}{w+s}]} \right\}^2} \\ \frac{\partial c}{\partial s}=-\frac{c_{\rm c}}{s^2} \\ \\ \end{cases} \end{equation}$

(17)

and

$w_{\rm opt} \geqslant s_{\rm min} \\ s_{\rm opt} \geqslant w_{\rm min } \\ s_{\rm min } +w_{\rm min } =pich_{\rm min} \\ $

(18)

The two equations are solved simultaneously by numerical techniques to determine the optimal solution.

5. Model verification and discussion

According to the interconnection parameters on 90 nm, 65 nm and 40 nm CMOS technologies in Table 2, the optimal results considering the self-heating effect can be compared with that without considering the self-heating effect to illustrate the necessity for considering the self-heating effect. From Figs. 3 and 5, we know that the small delay couples with low power dissipation. Thus, the simulation by setting $i$ $=$ 1, $j$ $=$ 0, $k$ $=$ 1 can be simplified. The simulation optimal results are given in Tables 3 and 4. The results corresponding to other $i, j$, and $k$ values can also be easily calculated just following the same simulation flow. In Tables 3 and 4, $w_{\rm opt}$, $s_{\rm opt}$, $h_{\rm opt}$, $k_{\rm opt}$, $\tau_{\rm opt}$, $P_{\rm opt}$ and $B_{\rm opt}$ are the optimal results with considering the self-heating effect, and $w^{\prime}_{\rm opt}$, $s^{\prime}_{\rm opt}$, $h^{\prime}_{\rm opt}$, $k^{\prime}_{\rm opt}$, $\tau^{\prime}_{\rm opt}$, $P^{\prime}_{\rm opt}$ and $B^{\prime}_{\rm opt}$ are the traditional optimization without considering the self-heating effect which is from Ref. [7].

By the analysis of Table 3, the optimal wire width $w_{\rm opt}$, wire spacing $s_{\rm opt}$, buffer size $k_{\rm opt}$ and the length $h_{\rm opt}$ between two buffers considering the self-heating effect is larger than that without considering the self-heating effect. This is mainly because the self-heating effect influences the interconnect resistance not only through the wire width, but also through the wire spacing. Larger $k$ and larger $h$ mean larger buffer size and less buffer number compared with that not considering self-heating are needed to achieve the best design. Therefore the self-heating effect can not be ignored.

In Table 4, the interconnection delay, power dissipation and bandwidth considering the self-heating effect achieve better optimization results than that without considering the self-heating effect. This is because the delay and bandwidth are affected even more by interconnection width and spacing in the case of considering the self-heating effect as illustrated in Figs. 3 and 4. Therefore, when the self-heating effect is considered, the less delay and larger bandwidth can be obtained. Figure 5 shows that larger wire width and spacing are required to fulfill the lower power dissipation, and in Table 3 the optimal width and spacing is wider when the self-heating effect is considered, hence the lower power dissipation obtained by considering the self-heating effect is more reasonable.

From all the analyses above, we can safely come to the conclusion that in the process of integrated circuits design, taking no consideration of the self-heating effect will have an adverse impact on the entire integrated circuit design, which is bound to lead to the variations of the circuit performance. Therefore the self-heating effect should be considered in the analysis of the performance of global interconnection.

6. Conclusion

Based on the inescapable impact of the self-heating effect, we improve the optimization buffer insertion model of interconnects by amending the optimal interconnection wire width and spacing. Firstly, the expression of the interconnect resistance per unit length versus interconnection wire width and spacing is given. Then, in the case of considering the self-heating effect, the interconnection wire delay, power dissipation and bandwidth, which depend on the interconnect resistance per unit length and capacitance, are analyzed. By analyzing the impact of the self-heating effect on interconnect delay, power dissipation and bandwidth, the FOM optimization model is presented on the basis of the trade-off theory. Finally, the proposed optimal model is validated and compared on 90 nm, 65 nm and 40 nm CMOS technologies. The modified optimization model is more accurate and realistic than traditional models and can be applied to CMOS integrated circuit interconnect optimal design.