1. Introduction
With the aggressive VLSI technology shrinking, an increasing number of interconnecting wire layers and a greater length of global interconnects are needed to diminish the design complexity, and the number of layers will reach 14 by 2017[1]. For this reason, the features of global interconnects such as delay, power dissipation and signal integrity are the main factors dominating the performance of a circuit. Consequently the global interconnect has become the center of the chip design flow[2-5]. Considering the fact that long global interconnects lead to a decline of the interconnect delay and signal integrity, buffer insertion techniques are adopted to reduce the defects of long global interconnects. As a result the number of buffers per chip reaches one billion in the end of the current decade[6].
In a practical application, the optimal buffer insertion technique gains much attention of researchers because of the wire sizing problem[2-18]. In Ref. [7] the interconnection wire width optimization method which depends on the wire spacing has been proposed for compromising interconnect power dissipation and delay. An optimal model to minimize interconnect power dissipation and area with constrains of target delay and target bandwidth is present in Ref. [8]. A methodology to include robustness optimization in power-delay optimal buffer insertion is proposed in Ref. [9]. However, these studies do not take into account the self-heating effects. In fact, since the global-tier interconnects are far away from the substrate attached to the heat sink, and the low dielectric constant materials with a low thermal conductivity widely used in VLSI circuit is adverse to the heat transfer, the metal self-heating caused by the flow of the current makes the temperature of global interconnects much higher than the die temperature[2, 3]. Therefore, as the interconnect resistance has a linear relationship with temperature, the self-heating effect greatly affects global interconnect performance and electro migration reliability. For nanometer high-performance circuits, ignoring self-heating effects may incur significant timing violations.
In this paper, a novel interconnect optimization methodology with consideration of the self-heating effect is proposed to systematically optimize the buffer insertion global interconnects. Firstly the expression of interconnection resistance per unit length with the consideration of the self-heating effect is deduced in nano-scales CMOS processes. Then the influences of the self-heating effect on the global interconnection delay, bandwidth and power dissipation are analyzed and an FOM optimization model which is tradeoff between delay, power dissipation and bandwidth is put forward. By solving the differential equations of FOM, the optimal interconnect wire width and spacing are obtained. Finally the proposed optimal model has been verified and compared on 90 nm, 65 nm and 40 nm CMOS technologies.
2. Self-heating effect model
In the current technologies of interconnection design, the heat generated by power dissipation
The temperature rise mainly increases the interconnect wire resistance per unit length, thereby deteriorating the interconnect performance. The wire resistance per unit length is inversely proportional to the interconnect wire width when the interconnect temperature is constant, and the expression is
The metal temperature
Tm=Tref+ΔTself−heating, |
(1) |
where
ΔTself−heating=(Tm−Tref)=1T∫T0I2rrθdt=I2rmsrrθ, |
(2) |
where
r=ρwH[1+βTm], |
(3) |
where
The thermal impedance of the per unit interconnection length to the substrate
rθ=12Kox(lnw+sw+2tox−sw+s), |
(4) |
where
Substitute Eqs. (2)-(4) into Eq. (1) the expression of
Tm=I2rmsρ(lnw+sw+2tox−sw+s) ×[2wHKox−I2rmsρβ(lnw+sw+2tox−sw+S)]-1. |
(5) |
Substituting Eq. (5) into Eq. (3), the expression of the interconnect resistance per unit length can be obtained as
r=2ρKox2wHKox−I2rmsρβ(lnw+Sw+2tox−sw+s). |
(6) |
According to Eq. (6), we can figure out the dependence of the interconnection resistance per unit length
The research in this paper is based on copper interconnection. Adopting the interconnect wire processing parameter and electric parameter accurately provided in Table 1, the variation of the normalized unit resistance
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3. Interconnection delay, power dissipation, bandwidth
Global interconnects with optimal number and size of inserted buffers are shown in Fig. 2, where
Assume that the length of a single buffer insertion segment line in a long global interconnect is
The Elmore delay distributed model is used to estimate the delay of global interconnects in this paper. So the delay of the line segment
τ=rs(c0+cp)+rskch+rhkc0+12rch2. |
(7) |
When the buffer size
k=kopt=√rscrc0, |
(8) |
h=hopt=√2rs(c0+cp)rc, |
(9) |
where the interconnection capacitance per unit length
c=ca+cbw+ccs, |
(10) |
where
The delay of the line segment is optimal. Therefore the optimal delay per unit length
(τh)opt=2√rsc0(1+√12(1+cpc0))√rc. |
(11) |
The total delay
D=L⋅ln2⋅(τh)opt. |
(12) |
For a single buffer insertion segment line in a long global interconnect, the power dissipation is composed of switching, short-circuit and leakage power. Suppose the power dissipation per unit length is
P=NLPrepeaterhopt=LchipLw+s[(m1+m3)(1+√12(1+cpc0))+m2√12c0(c0+cp)]c, |
(13) |
where
The global interconnection total delay
B=N1D=1ln2⋅2√rsc0(1+√12(1+cpc0))1√rc(w+s). |
(14) |
4. The global interconnection width and spacing optimization model considering the self-heating effect
The aim of global interconnection optimization is to obtain small delay per unit length, low power dissipation of the total global interconnection and large bandwidth. Since parameters
Based on the parameters in Table 2, the comparison of the normalized interconnection delay considering the self-heating effect to that without considering the self-heating effect is shown in Fig. 3, where
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Figure 4 shows the comparison of the normalized interconnection bandwidth considering self-heating effect with that without considering the self-heating effect. From Fig. 4, it is obvious that the maximum bandwidth can be obtained at
The global interconnection power distribution is inversely proportional to the width and spacing of the interconnection from Fig. 5 which is the same as that of the delay. So low power distribution requires large interconnection width and spacing.
The aim of the global interconnect design is to get a small delay per unit length, low power dissipation and large bandwidth simultaneously. Unfortunately, it can be seen from the above discussion, small delay
FOM=(τ/h)iPjBk, |
(15) |
where
According to Eqs. (6), (11) and (14), both the interconnect wire width
FOM∝(r(w,s))i+k2(c(w,s))i+k2+j(w+s)k, |
(16) |
which is a function of interconnection width and spacing. Setting the derivatives of FOM with respect to
{∂FOM∂w=(i+k2)(r(w,s))(i+k2−1)(c(w,s))(i+k2+j)(w+s)k∂r∂w+(i+k2+j)(r(w,s))(i+k2)(c(w,s))(i+k2+j−1)(w+s)k∂c∂w+k(r(w,s))(i+k2)(c(w,s))(i+k2+j)(w+s)k−1=0∂FOM∂s=(i+k2)(r(w,s))(i+k2−1)(c(w,s))(i+k2+j)(w+s)k∂r∂s+(i+k2+j)(r(w,s))(i+k2)(c(w,s))(i+k2+j−1)(w+s)k∂c∂s+k(r(w,s))(i+k2)(c(w,s))(i+k2+j)(w+s)k−1=0where∂r∂w=−2ρKox[2HKox+I2rmsρβ(2toxw+s2)(w+s)2w]{2wHKox−I2rmsρβ[lnw+sw+2tox−s2w+s]}2∂c∂w=cb∂r∂s=2ρKoxI2rmsρβ(2toxw+2w+s)(w+s)2{2wHKox−I2rmsρβ[lnw+sw+2tox−s2w+s]}2∂c∂s=−ccs2 |
(17) |
and
wopt⩾sminsopt⩾wminsmin+wmin=pichmin |
(18) |
The two equations are solved simultaneously by numerical techniques to determine the optimal solution.
5. Model verification and discussion
According to the interconnection parameters on 90 nm, 65 nm and 40 nm CMOS technologies in Table 2, the optimal results considering the self-heating effect can be compared with that without considering the self-heating effect to illustrate the necessity for considering the self-heating effect. From Figs. 3 and 5, we know that the small delay couples with low power dissipation. Thus, the simulation by setting
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By the analysis of Table 3, the optimal wire width
In Table 4, the interconnection delay, power dissipation and bandwidth considering the self-heating effect achieve better optimization results than that without considering the self-heating effect. This is because the delay and bandwidth are affected even more by interconnection width and spacing in the case of considering the self-heating effect as illustrated in Figs. 3 and 4. Therefore, when the self-heating effect is considered, the less delay and larger bandwidth can be obtained. Figure 5 shows that larger wire width and spacing are required to fulfill the lower power dissipation, and in Table 3 the optimal width and spacing is wider when the self-heating effect is considered, hence the lower power dissipation obtained by considering the self-heating effect is more reasonable.
From all the analyses above, we can safely come to the conclusion that in the process of integrated circuits design, taking no consideration of the self-heating effect will have an adverse impact on the entire integrated circuit design, which is bound to lead to the variations of the circuit performance. Therefore the self-heating effect should be considered in the analysis of the performance of global interconnection.
6. Conclusion
Based on the inescapable impact of the self-heating effect, we improve the optimization buffer insertion model of interconnects by amending the optimal interconnection wire width and spacing. Firstly, the expression of the interconnect resistance per unit length versus interconnection wire width and spacing is given. Then, in the case of considering the self-heating effect, the interconnection wire delay, power dissipation and bandwidth, which depend on the interconnect resistance per unit length and capacitance, are analyzed. By analyzing the impact of the self-heating effect on interconnect delay, power dissipation and bandwidth, the FOM optimization model is presented on the basis of the trade-off theory. Finally, the proposed optimal model is validated and compared on 90 nm, 65 nm and 40 nm CMOS technologies. The modified optimization model is more accurate and realistic than traditional models and can be applied to CMOS integrated circuit interconnect optimal design.