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J. Semicond. > 2013, Volume 34 > Issue 11 > 115004

SEMICONDUCTOR INTEGRATED CIRCUITS

A novel interconnect optimal buffer insertion model considering the self-heating effect

Yan Zhang, Gang Dong, Yintang Yang, Ning Wang, Yaoshun Ding, Xiaoxian Liu and Fengjuan Wang

+ Author Affiliations

 Corresponding author: Zhang Yan, zylap@aliyun.com

DOI: 10.1088/1674-4926/34/11/115004

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Abstract: Considering the self-heating effect, an accurate expression for the global interconnection resistance per unit length in terms of interconnection wire width and spacing is presented. Based on the proposed resistance model and according to the trade-off theory, a novel optimization analytical model of delay, power dissipation and bandwidth is derived. The proposed optimal model is verified and compared based on 90 nm, 65 nm and 40 nm CMOS technologies. It can be found that more optimum results can be easily obtained by the proposed model. This optimization model is more accurate and realistic than the conventional optimization models, and can be integrated into the global interconnection design of nano-scale integrated circuits.

Key words: self-heating effectinterconnection wire resistance per unit lengthoptimal modelvery large scale integration

With the aggressive VLSI technology shrinking, an increasing number of interconnecting wire layers and a greater length of global interconnects are needed to diminish the design complexity, and the number of layers will reach 14 by 2017[1]. For this reason, the features of global interconnects such as delay, power dissipation and signal integrity are the main factors dominating the performance of a circuit. Consequently the global interconnect has become the center of the chip design flow[2-5]. Considering the fact that long global interconnects lead to a decline of the interconnect delay and signal integrity, buffer insertion techniques are adopted to reduce the defects of long global interconnects. As a result the number of buffers per chip reaches one billion in the end of the current decade[6].

In a practical application, the optimal buffer insertion technique gains much attention of researchers because of the wire sizing problem[2-18]. In Ref. [7] the interconnection wire width optimization method which depends on the wire spacing has been proposed for compromising interconnect power dissipation and delay. An optimal model to minimize interconnect power dissipation and area with constrains of target delay and target bandwidth is present in Ref. [8]. A methodology to include robustness optimization in power-delay optimal buffer insertion is proposed in Ref. [9]. However, these studies do not take into account the self-heating effects. In fact, since the global-tier interconnects are far away from the substrate attached to the heat sink, and the low dielectric constant materials with a low thermal conductivity widely used in VLSI circuit is adverse to the heat transfer, the metal self-heating caused by the flow of the current makes the temperature of global interconnects much higher than the die temperature[2, 3]. Therefore, as the interconnect resistance has a linear relationship with temperature, the self-heating effect greatly affects global interconnect performance and electro migration reliability. For nanometer high-performance circuits, ignoring self-heating effects may incur significant timing violations.

In this paper, a novel interconnect optimization methodology with consideration of the self-heating effect is proposed to systematically optimize the buffer insertion global interconnects. Firstly the expression of interconnection resistance per unit length with the consideration of the self-heating effect is deduced in nano-scales CMOS processes. Then the influences of the self-heating effect on the global interconnection delay, bandwidth and power dissipation are analyzed and an FOM optimization model which is tradeoff between delay, power dissipation and bandwidth is put forward. By solving the differential equations of FOM, the optimal interconnect wire width and spacing are obtained. Finally the proposed optimal model has been verified and compared on 90 nm, 65 nm and 40 nm CMOS technologies.

In the current technologies of interconnection design, the heat generated by power dissipation I2R is removed through the substrate which is attached to the heat sink, and then the studies of the interconnect optimal model are always at a constant temperature[1-17]. The existing process corner files just consider the influences of the process fluctuations and the difference of interconnection on interconnect resistance and capacitance. However, since the interconnects, especially the global interconnects, are far away from the substrate and surrounded by low-k dielectrics with a lower thermal conductivity compared to the silicon dioxide, the heat generated cannot be efficiently removed and therefore causes an increase in interconnect temperature. So the self-heating effect is an inseparable aspect of electrical power distribution and signal transmission[19, 20].

The temperature rise mainly increases the interconnect wire resistance per unit length, thereby deteriorating the interconnect performance. The wire resistance per unit length is inversely proportional to the interconnect wire width when the interconnect temperature is constant, and the expression is r0 = ρ0/(wH), where ρ0 is the electrical resistivity of interconnect materials, w and H are the width and thickness of the interconnect wire, respectively. However, when the self-heating effect is considered, the interconnect unit resistance is related not only to the wire width but also to the spacing between any two wires. The new expression of the unit resistance is derived as follows.

The metal temperature Tm contains two parts and is given by[21]

Tm=Tref+ΔTselfheating,

(1)

where Tref is the reference temperature, and ΔTselfheatingis the temperature rise due to the self-heating effect. Here, we assume the thermal condition is, in most cases, steady. Then the temperature rise ΔTselfheating is given by

ΔTselfheating=(TmTref)=1TT0I2rrθdt=I2rmsrrθ,

(2)

where Irms is the root mean square current passing through the interconnect wire, I2rmsr represents the power dissipation on the interconnects, and r is the resistance per unit length, which has a linear relationship with interconnection temperature and can be written as below

r=ρwH[1+βTm],

(3)

where ρ is the electrical resistivity at the reference temperature Tref, and β is the temperature coefficient of resistance.

The thermal impedance of the per unit interconnection length to the substrate rθ can be expressed as

rθ=12Kox(lnw+sw+2toxsw+s),

(4)

where tox is the interconnect wire dielectric layer thickness, s is the interconnect wire spacing and Kox is the thermal conductivity of dielectric layers.

Substitute Eqs. (2)-(4) into Eq. (1) the expression of Tm can be obtained. Without loss of generality, Tm can reach up to 200 for global interconnects[22], and Tref is the ambient temperature. So Tref can be ignored and Tm is expressed by

Tm=I2rmsρ(lnw+sw+2toxsw+s)      ×[2wHKoxI2rmsρβ(lnw+sw+2toxsw+S)]-1.

(5)

Substituting Eq. (5) into Eq. (3), the expression of the interconnect resistance per unit length can be obtained as

r=2ρKox2wHKoxI2rmsρβ(lnw+Sw+2toxsw+s).

(6)

According to Eq. (6), we can figure out the dependence of the interconnection resistance per unit length r on both the interconnect wire width w and the spacing between any tow wire s.

The research in this paper is based on copper interconnection. Adopting the interconnect wire processing parameter and electric parameter accurately provided in Table 1, the variation of the normalized unit resistance r/r0 with the interconnect width and spacing is shown in Fig. 1 for a global interconnection with buffer insertion on 40 nm technology, where r0 is obtained at the condition of w=s=wmin. Obviously, r varies inversely with w and s, respectively. Figure 1 also shows that r varies very abruptly with the interconnect wire spacing than with the interconnect wire width. It is because the distribution of metal temperature is depended not only on the interconnect wire width but also on the interconnect wire spacing in Eq. (5). Hence the resistance per unit length affected by the temperature is also dependent on the interconnect wire width and the interconnect wire spacing. So the influence of the interconnect spacing on the interconnection resistance per unit length r can not be neglected.

Table  1.  The interconnection wire processing parameter and electric parameter of 40 nm[1].
DownLoad: CSV  | Show Table
Figure  1.  The variation of r with w and s.

Global interconnects with optimal number and size of inserted buffers are shown in Fig. 2, where Lchip is the chip width for global interconnects and L is the interconnect length. w+s is the global interconnect pitch. Here we assumed that all the global interconnects have the same wire width and wire spacing, then the number of global interconnects N is equal to Lchip/(w+s).

Figure  2.  Global interconnects with optimal buffer insertion.

Assume that the length of a single buffer insertion segment line in a long global interconnect is h, and the interconnect capacitance per unit length is c. For a minimum size buffer, the input capacitance, output capacitance and output resistance are c0, cp and rs respectively. Suppose the buffer size is k, then the input capacitance, output capacitance and output resistance is kc0, kcp and rs/k respectively.

The Elmore delay distributed model is used to estimate the delay of global interconnects in this paper. So the delay of the line segment τ is described as[16, 17]

τ=rs(c0+cp)+rskch+rhkc0+12rch2.

(7)

When the buffer size k and the length h satisfy the following equations:

k=kopt=rscrc0,

(8)

h=hopt=2rs(c0+cp)rc,

(9)

where the interconnection capacitance per unit length c can be written as

c=ca+cbw+ccs,

(10)

where ca represents the fringing capacitance, cb represents the parallel plate capacitance to the top and bottom layers of metal and cc represents the coupling capacitance between the neighboring interconnects.

The delay of the line segment is optimal. Therefore the optimal delay per unit length (τ/h)opt can be obtained from Eqs. (7)-(9) as

(τh)opt=2rsc0(1+12(1+cpc0))rc.

(11)

The total delay D of global interconnects is

D=Lln2(τh)opt.

(12)

For a single buffer insertion segment line in a long global interconnect, the power dissipation is composed of switching, short-circuit and leakage power. Suppose the power dissipation per unit length is Prepeater/hopt, so the total power of global interconnects is

P=NLPrepeaterhopt=LchipLw+s[(m1+m3)(1+12(1+cpc0))+m212c0(c0+cp)]c,

(13)

where m1=αfV2dd, m2=32V2ddIoffnfwnmin, m3=2ln3V2ddIshortcircuitfwnmin, and α is the switching activity factor which can be taken as 0.15, f is the clock frequency, Vdd is the power supply voltage, Ioff is the leakage current of NMOS n-channel, wnmin is the width of the NMOS transistor in a minimum sized inverter. Ishortcurcuit is the short circuit current per transistor width and the normal value is 65 μA/μm.

The global interconnection total delay D and the number of interconnects N decide the interconnect bandwidth. The bandwidth B with the optimal buffer insertion shown in Fig. 2 can be defined as

B=N1D=1ln22rsc0(1+12(1+cpc0))1rc(w+s).

(14)

The aim of global interconnection optimization is to obtain small delay per unit length, low power dissipation of the total global interconnection and large bandwidth. Since parameters r and c are functions of the interconnection width w and spacing s expressed in Eqs. (6) and (10) respectively, from Eqs. (11), (13) and (14), the variation tendency of the delay, power dissipation and bandwidth with the interconnection width w and spacing s can be depicted by plotting.

Based on the parameters in Table 2, the comparison of the normalized interconnection delay considering the self-heating effect to that without considering the self-heating effect is shown in Fig. 3, where τ0 is obtained at the condition of w=s=wmin. It can be seen from Fig. 3 that the delay decreases with the increase of interconnection wire width and spacing, while the error of the delay becomes greater. Figure 3 also shows that the curved surface of interconnection delay considering the self-heating effect varies much more abruptly with the interconnection wire width and spacing than that of no consideration of the self-heating effect.

Table  2.  The interconnection parameters at 90 nm, 65 nm and 40nm CMOS technologies[1].
DownLoad: CSV  | Show Table
Figure  3.  The comparison of interconnection delay considering the self-heating effect and not considering the self-heating effect.

Figure 4 shows the comparison of the normalized interconnection bandwidth considering self-heating effect with that without considering the self-heating effect. From Fig. 4, it is obvious that the maximum bandwidth can be obtained at w=wmin, s=smin without considering the self-heating effect, but in the case of considering the self-heating effect, the maximum bandwidth is obtained at w=wmin, s=asmin, where 1 < a < 2. The error of the wire spacing at which the maximum bandwidth is achieved is great, thus is bound to lead to the error of the performance which can not be ignored and further affects the entire integrated circuit design. Therefore the self-heating effect is hard to consider when the performance of interconnection wires is analyzed.

Figure  4.  The comparison of interconnection bandwidth considering the self-heating effect and not considering the self-heating effect.

The global interconnection power distribution is inversely proportional to the width and spacing of the interconnection from Fig. 5 which is the same as that of the delay. So low power distribution requires large interconnection width and spacing.

Figure  5.  The interconnection power versus the interconnection width and spacing.

The aim of the global interconnect design is to get a small delay per unit length, low power dissipation and large bandwidth simultaneously. Unfortunately, it can be seen from the above discussion, small delay τ and low power dissipation P require large interconnection width and spacing, but large bandwidth B requires small interconnection width and spacing. Therefore, a trade-off among the delay, power dissipation and the bandwidth can be used as an FOM model:

FOM=(τ/h)iPjBk,

(15)

where i, j and k are the weight of the cost functions which can be any positive real numbers. The weights i, j and kimply which design objective is more highly valued. i=j=k indicates that the delay, power dissipation and bandwidth are valued the same in the global interconnection design, while i > j=k indicates that the delay is more important than the power dissipation and bandwidth. The values of i, j and k can be chosen according to the design requirements.

According to Eqs. (6), (11) and (14), both the interconnect wire width w and the spacing between any tow wire s decide the interconnection resistance per unit length r considering the self-heating effect and furthermore affect the interconnection delay and bandwidth. So FOM has the following property:

FOM(r(w,s))i+k2(c(w,s))i+k2+j(w+s)k,

(16)

which is a function of interconnection width and spacing. Setting the derivatives of FOM with respect to w and s to be zero, the minimum values by solving the partial differential equations can be obtained, which means the optimal width and spacing is gained.

{FOMw=(i+k2)(r(w,s))(i+k21)(c(w,s))(i+k2+j)(w+s)krw+(i+k2+j)(r(w,s))(i+k2)(c(w,s))(i+k2+j1)(w+s)kcw+k(r(w,s))(i+k2)(c(w,s))(i+k2+j)(w+s)k1=0FOMs=(i+k2)(r(w,s))(i+k21)(c(w,s))(i+k2+j)(w+s)krs+(i+k2+j)(r(w,s))(i+k2)(c(w,s))(i+k2+j1)(w+s)kcs+k(r(w,s))(i+k2)(c(w,s))(i+k2+j)(w+s)k1=0whererw=2ρKox[2HKox+I2rmsρβ(2toxw+s2)(w+s)2w]{2wHKoxI2rmsρβ[lnw+sw+2toxs2w+s]}2cw=cbrs=2ρKoxI2rmsρβ(2toxw+2w+s)(w+s)2{2wHKoxI2rmsρβ[lnw+sw+2toxs2w+s]}2cs=ccs2

(17)

and

woptsminsoptwminsmin+wmin=pichmin

(18)

The two equations are solved simultaneously by numerical techniques to determine the optimal solution.

According to the interconnection parameters on 90 nm, 65 nm and 40 nm CMOS technologies in Table 2, the optimal results considering the self-heating effect can be compared with that without considering the self-heating effect to illustrate the necessity for considering the self-heating effect. From Figs. 3 and 5, we know that the small delay couples with low power dissipation. Thus, the simulation by setting i = 1, j = 0, k = 1 can be simplified. The simulation optimal results are given in Tables 3 and 4. The results corresponding to other i,j, and k values can also be easily calculated just following the same simulation flow. In Tables 3 and 4, wopt, sopt, hopt, kopt, τopt, Popt and Bopt are the optimal results with considering the self-heating effect, and wopt, sopt, hopt, kopt, τopt, Popt and Bopt are the traditional optimization without considering the self-heating effect which is from Ref. [7].

Table  3.  Comparison of interconnect dimension parameters between two kinds of optimization results.
DownLoad: CSV  | Show Table
Table  4.  Comparison of interconnect delay, power dissipation and bandwidth between two kinds of optimization results.
DownLoad: CSV  | Show Table

By the analysis of Table 3, the optimal wire width wopt, wire spacing sopt, buffer size kopt and the length hopt between two buffers considering the self-heating effect is larger than that without considering the self-heating effect. This is mainly because the self-heating effect influences the interconnect resistance not only through the wire width, but also through the wire spacing. Larger k and larger h mean larger buffer size and less buffer number compared with that not considering self-heating are needed to achieve the best design. Therefore the self-heating effect can not be ignored.

In Table 4, the interconnection delay, power dissipation and bandwidth considering the self-heating effect achieve better optimization results than that without considering the self-heating effect. This is because the delay and bandwidth are affected even more by interconnection width and spacing in the case of considering the self-heating effect as illustrated in Figs. 3 and 4. Therefore, when the self-heating effect is considered, the less delay and larger bandwidth can be obtained. Figure 5 shows that larger wire width and spacing are required to fulfill the lower power dissipation, and in Table 3 the optimal width and spacing is wider when the self-heating effect is considered, hence the lower power dissipation obtained by considering the self-heating effect is more reasonable.

From all the analyses above, we can safely come to the conclusion that in the process of integrated circuits design, taking no consideration of the self-heating effect will have an adverse impact on the entire integrated circuit design, which is bound to lead to the variations of the circuit performance. Therefore the self-heating effect should be considered in the analysis of the performance of global interconnection.

Based on the inescapable impact of the self-heating effect, we improve the optimization buffer insertion model of interconnects by amending the optimal interconnection wire width and spacing. Firstly, the expression of the interconnect resistance per unit length versus interconnection wire width and spacing is given. Then, in the case of considering the self-heating effect, the interconnection wire delay, power dissipation and bandwidth, which depend on the interconnect resistance per unit length and capacitance, are analyzed. By analyzing the impact of the self-heating effect on interconnect delay, power dissipation and bandwidth, the FOM optimization model is presented on the basis of the trade-off theory. Finally, the proposed optimal model is validated and compared on 90 nm, 65 nm and 40 nm CMOS technologies. The modified optimization model is more accurate and realistic than traditional models and can be applied to CMOS integrated circuit interconnect optimal design.



[1]
Semiconductor Industry Association 2012 International Technology Roadmap for Semiconductors 2012(ITRS 2012)
[2]
Chen G Q, Friedman E G. Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints. IEEE Trans Very Large Scale Integr Syst, 2006, 14(2):161 doi: 10.1109/TVLSI.2005.863750
[3]
Abinash R, Chowdhury M H. Global interconnect optimization in the presence of on-chip inductance. IEEE International Symposium on Circuits and Systems, 2007:885 http://ieeexplore.ieee.org/document/4252777/?arnumber=4252777&contentType=Conference%20Publications
[4]
Faiz-ul-Hassan, Fernando R, Vanderbauwhede W A. Optimization of on-chip link performance under area, power and variability constraints. 22nd International Conference on Microelectronics, 2010:48 http://ieeexplore.ieee.org/document/5696196/?arnumber=5696196&punumber%3D5686267
[5]
Zhu Z M, Wan D J, Yang Y T. An interconnect width and spacing optimization model considering scattering effect. Chin Phys B, 2010, 19(9):097803 doi: 10.1088/1674-1056/19/9/097803
[6]
Vinita V D, Jeffrey A D. Optimal voltage scaling, repeater insertion, and wire sizing for wave-pipelined global interconnects. IEEE Trans Circuits Syst Ⅰ:Fundamental Theory and Applications, 2008, 55(4):1023 doi: 10.1109/TCSI.2008.916506
[7]
Tang M, Mao J F. Wire sizing optimization for buffered global interconnects. International Conference on Microwave and Millimeter Wave Technology, 2008:431 http://ieeexplore.ieee.org/document/4540430/
[8]
Zhu Z M, Zhong B, He B T. A novel nanometer CMOS interconnect optimal model with target delay and bandwidth constraint. Acta Phys Sin, 2010, 59(3):1997
[9]
Ashok N, Ramalingam S. Variability aware low-power delay optimal buffer insertion for global interconnects. IEEE Trans Circuits Syst Ⅰ, Reg Pap, 2010, 57(12):3055 doi: 10.1109/TCSI.2010.2073790
[10]
Fargol H, Nasser M. Interconnect sizing and spacing with consideration of buffer insertion for simultaneous crosstalk-delay optimization. IEEE International Conference on Design and Test of Integrated Systems in Nanoscale Era, 2008:12008 http://ieeexplore.ieee.org/document/4540218/keywords
[11]
Renatas J, Friedman E G. Resource based optimization for simultaneous shield and repeater insertion. IEEE Trans Very Large Scale Integr Syst, 2010, 18(5):742 doi: 10.1109/TVLSI.2009.2015950
[12]
Mahmoud Z, Nasser M. Throughput optimization for interleaved repeater-inserted interconnects in VLSI design. IEEE 3rd International Nanoelectronics Conference, 2010:1 http://ieeexplore.ieee.org/document/5424802/?reload=true&arnumber=5424802&punumber%3D5416830
[13]
Houman Z, Asim A, Yvon S. Repeater insertion in power-managed VLSI systems. Proc ACM Great Lakes Symp VLSI GLSVLSI, 2011:395 http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2011.html
[14]
Massimo A, Stephane B, Yusuf L. Optimization of the wire grid size for differential routing:analysis and impact on the power-delay-area tradeoff. Microelectron J, 2010, 41:669 doi: 10.1016/j.mejo.2010.06.005
[15]
Sandeep S A, Mahesh K, Sreehari V. An Alternative approach to buffer insertion for delay and power reduction in VLSI interconnects. 23rd International Conference on VLSI Design, 2010:441 http://ieeexplore.ieee.org/document/5401211/?arnumber=5401211
[16]
Zhu Z M, Wan D J, Yang Y T. An optimization model of wire size for multi-objective constrain. Acta Phys Sin, 2009, 59(7):4838 http://d.wanfangdata.com.cn/Periodical_wlxb201007067.aspx
[17]
Liu J, Dong G, Xue M, et al. Performance optimization of global interconnect based on dual supply and dual threshold voltages. Acta Phys Sin, 2012, 60(4):046602
[18]
Zhu Z M, Qian L B, Yang Y T, et al. A novel interconnect-optimal repeater insertion model with a target delay constraint. Journal of Semiconductors, 2008, 20(4):1847 http://www.jos.ac.cn/bdtxbcn/ch/reader/view_abstract.aspx?file_no=08010601&flag=1
[19]
Banafsheh B Y K, Joshi S K. Interconnect joule heating under transient currents using the transmission line matrix method. J Electron Packaging, 2012, 139:011009 http://electronicpackaging.asmedigitalcollection.asme.org/article.aspx?articleid=1410141&resultClick=1
[20]
Yokogawa S, Kakuhara Y, Tsuchiya H. Joule heating effects on electromigration in Cu/low-k interconnects. IEEE International Reliability Physics Symposium Proceedings, 2009:837
[21]
Ni M, Memik S O M. Self-heating aware optimal wire sizing under Elmore delay model. Proc Des Autom Test Eur. DATE Nice Acropolis, 2007:1373 http://ieeexplore.ieee.org/document/4211999/
[22]
Ajami A H, Banerjee K, Pedram M. Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects. IEEE Trans Comput Aided Des Integr Circuits Syst, 2005, 24(6):849 doi: 10.1109/TCAD.2005.847944
Fig. 1.  The variation of r with w and s.

Fig. 2.  Global interconnects with optimal buffer insertion.

Fig. 3.  The comparison of interconnection delay considering the self-heating effect and not considering the self-heating effect.

Fig. 4.  The comparison of interconnection bandwidth considering the self-heating effect and not considering the self-heating effect.

Fig. 5.  The interconnection power versus the interconnection width and spacing.

Table 1.   The interconnection wire processing parameter and electric parameter of 40 nm[1].

Table 2.   The interconnection parameters at 90 nm, 65 nm and 40nm CMOS technologies[1].

Table 3.   Comparison of interconnect dimension parameters between two kinds of optimization results.

Table 4.   Comparison of interconnect delay, power dissipation and bandwidth between two kinds of optimization results.

[1]
Semiconductor Industry Association 2012 International Technology Roadmap for Semiconductors 2012(ITRS 2012)
[2]
Chen G Q, Friedman E G. Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints. IEEE Trans Very Large Scale Integr Syst, 2006, 14(2):161 doi: 10.1109/TVLSI.2005.863750
[3]
Abinash R, Chowdhury M H. Global interconnect optimization in the presence of on-chip inductance. IEEE International Symposium on Circuits and Systems, 2007:885 http://ieeexplore.ieee.org/document/4252777/?arnumber=4252777&contentType=Conference%20Publications
[4]
Faiz-ul-Hassan, Fernando R, Vanderbauwhede W A. Optimization of on-chip link performance under area, power and variability constraints. 22nd International Conference on Microelectronics, 2010:48 http://ieeexplore.ieee.org/document/5696196/?arnumber=5696196&punumber%3D5686267
[5]
Zhu Z M, Wan D J, Yang Y T. An interconnect width and spacing optimization model considering scattering effect. Chin Phys B, 2010, 19(9):097803 doi: 10.1088/1674-1056/19/9/097803
[6]
Vinita V D, Jeffrey A D. Optimal voltage scaling, repeater insertion, and wire sizing for wave-pipelined global interconnects. IEEE Trans Circuits Syst Ⅰ:Fundamental Theory and Applications, 2008, 55(4):1023 doi: 10.1109/TCSI.2008.916506
[7]
Tang M, Mao J F. Wire sizing optimization for buffered global interconnects. International Conference on Microwave and Millimeter Wave Technology, 2008:431 http://ieeexplore.ieee.org/document/4540430/
[8]
Zhu Z M, Zhong B, He B T. A novel nanometer CMOS interconnect optimal model with target delay and bandwidth constraint. Acta Phys Sin, 2010, 59(3):1997
[9]
Ashok N, Ramalingam S. Variability aware low-power delay optimal buffer insertion for global interconnects. IEEE Trans Circuits Syst Ⅰ, Reg Pap, 2010, 57(12):3055 doi: 10.1109/TCSI.2010.2073790
[10]
Fargol H, Nasser M. Interconnect sizing and spacing with consideration of buffer insertion for simultaneous crosstalk-delay optimization. IEEE International Conference on Design and Test of Integrated Systems in Nanoscale Era, 2008:12008 http://ieeexplore.ieee.org/document/4540218/keywords
[11]
Renatas J, Friedman E G. Resource based optimization for simultaneous shield and repeater insertion. IEEE Trans Very Large Scale Integr Syst, 2010, 18(5):742 doi: 10.1109/TVLSI.2009.2015950
[12]
Mahmoud Z, Nasser M. Throughput optimization for interleaved repeater-inserted interconnects in VLSI design. IEEE 3rd International Nanoelectronics Conference, 2010:1 http://ieeexplore.ieee.org/document/5424802/?reload=true&arnumber=5424802&punumber%3D5416830
[13]
Houman Z, Asim A, Yvon S. Repeater insertion in power-managed VLSI systems. Proc ACM Great Lakes Symp VLSI GLSVLSI, 2011:395 http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2011.html
[14]
Massimo A, Stephane B, Yusuf L. Optimization of the wire grid size for differential routing:analysis and impact on the power-delay-area tradeoff. Microelectron J, 2010, 41:669 doi: 10.1016/j.mejo.2010.06.005
[15]
Sandeep S A, Mahesh K, Sreehari V. An Alternative approach to buffer insertion for delay and power reduction in VLSI interconnects. 23rd International Conference on VLSI Design, 2010:441 http://ieeexplore.ieee.org/document/5401211/?arnumber=5401211
[16]
Zhu Z M, Wan D J, Yang Y T. An optimization model of wire size for multi-objective constrain. Acta Phys Sin, 2009, 59(7):4838 http://d.wanfangdata.com.cn/Periodical_wlxb201007067.aspx
[17]
Liu J, Dong G, Xue M, et al. Performance optimization of global interconnect based on dual supply and dual threshold voltages. Acta Phys Sin, 2012, 60(4):046602
[18]
Zhu Z M, Qian L B, Yang Y T, et al. A novel interconnect-optimal repeater insertion model with a target delay constraint. Journal of Semiconductors, 2008, 20(4):1847 http://www.jos.ac.cn/bdtxbcn/ch/reader/view_abstract.aspx?file_no=08010601&flag=1
[19]
Banafsheh B Y K, Joshi S K. Interconnect joule heating under transient currents using the transmission line matrix method. J Electron Packaging, 2012, 139:011009 http://electronicpackaging.asmedigitalcollection.asme.org/article.aspx?articleid=1410141&resultClick=1
[20]
Yokogawa S, Kakuhara Y, Tsuchiya H. Joule heating effects on electromigration in Cu/low-k interconnects. IEEE International Reliability Physics Symposium Proceedings, 2009:837
[21]
Ni M, Memik S O M. Self-heating aware optimal wire sizing under Elmore delay model. Proc Des Autom Test Eur. DATE Nice Acropolis, 2007:1373 http://ieeexplore.ieee.org/document/4211999/
[22]
Ajami A H, Banerjee K, Pedram M. Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects. IEEE Trans Comput Aided Des Integr Circuits Syst, 2005, 24(6):849 doi: 10.1109/TCAD.2005.847944
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    Yan Zhang, Gang Dong, Yintang Yang, Ning Wang, Yaoshun Ding, Xiaoxian Liu, Fengjuan Wang. A novel interconnect optimal buffer insertion model considering the self-heating effect[J]. Journal of Semiconductors, 2013, 34(11): 115004. doi: 10.1088/1674-4926/34/11/115004
    Y Zhang, G Dong, Y T Yang, N Wang, Y S Ding, X X Liu, F J Wang. A novel interconnect optimal buffer insertion model considering the self-heating effect[J]. J. Semicond., 2013, 34(11): 115004. doi: 10.1088/1674-4926/34/11/115004.
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    Received: 29 March 2013 Revised: 09 June 2013 Online: Published: 01 November 2013

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      Yan Zhang, Gang Dong, Yintang Yang, Ning Wang, Yaoshun Ding, Xiaoxian Liu, Fengjuan Wang. A novel interconnect optimal buffer insertion model considering the self-heating effect[J]. Journal of Semiconductors, 2013, 34(11): 115004. doi: 10.1088/1674-4926/34/11/115004 ****Y Zhang, G Dong, Y T Yang, N Wang, Y S Ding, X X Liu, F J Wang. A novel interconnect optimal buffer insertion model considering the self-heating effect[J]. J. Semicond., 2013, 34(11): 115004. doi: 10.1088/1674-4926/34/11/115004.
      Citation:
      Yan Zhang, Gang Dong, Yintang Yang, Ning Wang, Yaoshun Ding, Xiaoxian Liu, Fengjuan Wang. A novel interconnect optimal buffer insertion model considering the self-heating effect[J]. Journal of Semiconductors, 2013, 34(11): 115004. doi: 10.1088/1674-4926/34/11/115004 ****
      Y Zhang, G Dong, Y T Yang, N Wang, Y S Ding, X X Liu, F J Wang. A novel interconnect optimal buffer insertion model considering the self-heating effect[J]. J. Semicond., 2013, 34(11): 115004. doi: 10.1088/1674-4926/34/11/115004.

      A novel interconnect optimal buffer insertion model considering the self-heating effect

      DOI: 10.1088/1674-4926/34/11/115004
      Funds:

      the Key Science & Technology Special Project of Shaanxi Province, China 2011KTCQ01-19

      Project supported by the National Natural Science Foundation of China (No. 60606006), the Key Science & Technology Special Project of Shaanxi Province, China (No. 2011KTCQ01-19), and the National Defense Pre-Research Foundation of China (No. 9140A23060111)

      the National Natural Science Foundation of China 60606006

      the National Defense Pre-Research Foundation of China 9140A23060111

      More Information
      • Corresponding author: Zhang Yan, zylap@aliyun.com
      • Received Date: 2013-03-29
      • Revised Date: 2013-06-09
      • Published Date: 2013-11-01

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