1. Introduction

Continuous research efforts have been made on W-band (75-110 GHz) amplifier MMICs because of their future potential applications, such as essential components of millimeter regional radars and passive imagers. InP-based high electron mobility transistors (HEMTs) have been highlighted in various millimeter-wave applications^[1-3] due to their excellent performance in terms of noise figure, gain, cut-off frequency, and power-added efficiency. A great number of excellent amplifier MMICs operating in W-band frequencies have been reported based on InP HEMT technology^{[4, 5]}. These circuits benefit from a greatly enhanced device technology process as well as an extraordinarily elaborate layout design.

The cascode configuration consists of common-source and common-gate HEMTs, providing superior gain performance as compared with traditional common-source structures. Some additional advantages, such as significantly higher output impedance, improved reverse isolation, and drastically reduced Miller feedback capacitance, make the cascode configuration a preferred technique for use in different amplifier circuits^[6-8].

The coplanar waveguide (CPW) propagation medium is extensively utilized for high frequency applications, especially for cascode configurations, due to the compatible interdigitated layout of the HEMT device with a CPW propagation medium. Additionally, compared to micro-strips, a well-designed millimeter-wave CPW has the advantages of lower dispersion, lower radiation losses, lower substrate thickness sensitivity, lower-inductance and easier ground plane access, being uniplanar, and simplified fabrication without backside processing. The ground-to-ground spacing of a CPW depends on the trade-off between its various parameters such as dispersion, losses, and substrate thickness sensitivity.

In this work, a W-band two-stage amplifier MMIC is reported with a small-signal gain of 25.7 dB at 106 GHz. The amplifier is implemented based on InP HEMT technology with $f_{\rm T}$ $=$ 165 GHz and $f_{\rm max}$ $=$ 295 GHz. A cascode configuration in combination with CPW technology is adopted in the design. These results indicate that InP HEMT technology has a great potential for W-band applications.

2. InP HEMT technology

The W-band amplifier MMIC was fabricated using an InAlAs/InGaAs material structure grown by molecular beam epitaxy (MBE) on a 3-inch semi-insulating InP substrate. The MMIC process steps started at mesa isolation by means of a phosphorus acid-based wet chemical etching to expose the In$_{0.52}$Al$_{0.48}$As buffer layer. Composite InGaAs cap layers consisting of a Si-doped In$_{0.6}$Ga$_{0.4}$As cap layer and a Si-doped In$_{0.53}$Ga$_{0.47}$As transition layer were capped in sequence to reduce the Ohmic contact resistance. Subsequently, 0.15 $\mu$m T-shaped gates were defined by e-beam lithography and the gate recess was formed by phosphorus acid/hydrogen peroxide wet etching till the InP etching-stopper layer, which served as a surface passivation layer for avoiding the kink-effect in DC characteristics. Figure 1 shows a schematic cross-section of the fabricated InP HEMTs. Finally, 200 nm silicon nitride was deposited by plasma-enhanced chemical vapor deposition (PECVD) to passivate the devices to achieve good reliability and robustness. The process further included 50 $\Omega$/$\square$ TaN thin film resistors (TFRs), 0.3 fF/$\mu$m$^{2}$ metal-insulator-metal (MIM) capacitors, and two levels of metal interconnects with a 2.7-$\mu$m-thick plated Au layer air bridge. Air bridges were used at each CPW discontinuity to suppress undesired slot mode excitation. Figure 2 is a scanning electron microscope (SEM) photograph showing the component details in CPW technology.

Transmission line method (TLM) measurements revealed a contact resistance of 0.032 $\Omega$$\cdot$mm and a specific contact resistivity of 1.03 $\times$ 10$^{-7}$ $\Omega$/cm$^{2}$ on the linear TLM patterns. Thus, the maximum extrinsic transconductance ($g_{\rm m, max})$ of 821 mS/mm was markedly enhanced by the superb Ohmic contact. Also the maximum channel current ($I_{\rm D, max})$ of 409.3 mA/mm measured at the drain-source voltage ($V_{\rm DS})$ of 2.0 V is illustrated in Fig. 3.

By using a lattice matched In$_{0.53}$Ga$_{0.47}$As channel, an off-state gate-drain breakdown voltage of over 4 V was obtained. The output conductance was also well controlled by a carefully optimized gate recess etching process and an epitaxial structure design. The current gain cutoff frequency ($f_{\rm T})$ of 165 GHz and the maximum oscillation frequency ($f_{\rm max})$ of 295 GHz are demonstrated in Fig. 4. The device technology has sufficiently satisfied the designs in W-band frequencies.

3. Amplifier design

In millimeter-wave frequencies, the feedback capacitance and output impedance are significantly improved for cascode configurations as compared with that for standard common-source devices. Firstly, the common-gate device reduces the impedance seen at the drain terminal of common-source devices, thereby reducing the Miller feedback capacitance of the common-source device. Secondly, the series combination of common-source gate-to-drain capacitance ($C_{\rm gd1})$ and common-gate drain-to-source capacitance ($C_{\rm ds2})$ ensures lower output-input feedback capacitance. Additionally, $C_{\rm gd2}$ is lower than $C_{\rm ds}$ in general, which improves the output impedance for cascode configurations.

The maximum available gain of a field-effect transistor in millimeter-wave frequencies is strongly affected by the feedback capacitance and output conductance, as expressed in Eq. (1). So it makes sense that the cascode structure shows superior gain performance.

$\begin{array}{l} {G_{{\rm{max}}}} \cong {\left( {\frac{{{f_{\rm{T}}}}}{f}} \right)^2}\\ \;\;\;\;\;\;\;\;\; = \frac{1}{{4[{g_{{\rm{ds}}}}(\Sigma r + \pi {f_{\rm{T}}}{L_{\rm{s}}}) + \pi {f_{\rm{T}}}{C_{{\rm{gd}}}}(\Sigma r + {r_{\rm{g}}} + \pi {f_{\rm{T}}}{L_{\rm{s}}})]}}, \\ \;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\Sigma r = {r_{\rm{g}}} + {r_{{\rm{gs}}}} + {r_{\rm{s}}}. \end{array}$

(1)

The schematic diagram of the two-stage W-band amplifier is shown in Fig. 5. Two 0.15 $\mu$m gate-length HEMTs with gate-width of 2 $\times$ 20 $\mu$m each are utilized in common-source and common-gate configuration. The devices biased at the peak transconductance point with $V_{\rm GS}$ $=$ 0.2 V. The amplifier architecture comprises a cascode core, bias lines, input matching, inter-stage matching, and output matching.

The cascode structure requires less chip-size per unit gain, however, it is more difficult to stabilize, due to $S_{22}$ usually being larger than 1 at high frequencies. An inductive element as an inter-stage network and a capacitive element in the gate line of the common-gate HEMT are proved to be effective for stabilizing the amplifier circuit.

The circuit design task is started by a cascode cell part with the goal of jointly obtaining superior gain and stability in the operating frequencies. Secondly, the input and output are separately matched for 50 $\Omega$ impedance using open stub networks. Thirdly, the inter-stage matching is optimized for maximum gain with an inter-digital coupling capacitor blocking low frequency signal, and thus enhancing the stability of amplifier. The bias lines are designed with quarter-wave short stubs at a center frequency of 94 GHz, and the bypass MIM capacitors short-out these quarter-wave lines in-band and isolate the rest of the amplifier from the power supply. In addition, TFRs and capacitors are included in the bias networks for improving stability.

During the sub-module simulation, the passive elements including capacitances, resistors, and CPWs in the schematic circuit are optimized to reach a compromise between gain and stability in the Agilent advanced design system (ADS). Especially, the inter-HEMT inductive peaking, the RF-grounding capacitance of the common-gate device, and the bypass MIM capacitors in the bias lines are given consideration above all else in the optimization process. Importantly, the stability factor is given a higher weight to ensure circuit probability by sacrificing some gain in the operating frequencies. The simulated Rollett stability factor $K$ for the amplifier is greater than 1 for all frequencies between DC and 100 GHz.

After schematic designing, the matching and bias networks are separately modeled utilizing an electromagnetic (EM) simulator of Momentum in ADS, to consider the distributed effect of the passive components. Ultimately, the entire designed circuit was EM-simulated. Figure 6 shows the chip photograph of the realized two-stage amplifier MMIC. The compact coplanar layout resulted in a small over-all chip-size of 1.85 $\times$ 0.932 mm$^{2}$. Limited by the actual air-bridge technology process, all CPW elements have a fixed ground-to-ground spacing of 50 $\mu$m.

4. Measurements and discussion

The small-signal characteristics of the amplifier was measured by using an HP8510C vector network analyzer (VNA) and a 41st Institute of China Electronics Technology Group Corporation W-band system on SUSS semi-automatic probe station. A block diagram of the power performance test setup is shown in Fig. 7. The power measurements have been performed using a Farran Tech doubler frequency source and W-band power meter of the 41st Institute. The output power of the W-band frequency source was set to be the maximum value of 5 dBm. A fixed attenuator of $-20$ dB and an adjustable attenuator with maximum attenuation of $-20$ dB were used to regulate the input signal for the amplifier. The two-stage amplifier was biased under $V_{\rm D1}$ $=$ $V_{\rm D2}$ $=$ 4.0 V, $V_{\rm G11}$ $=$ $V_{\rm G12}$ $=$ 0.2 V, $V_{\rm G2}$ $=$ 2 V for maximum gain.

Simulated and measured $S$-parameters are depicted in Figs. 8(a) and 8(b), respectively. The simulated maximum gain is approximately 26.6 dB at 97 GHz with 3 dB bandwidth from 86 to 99 GHz, while the measured maximum gain is about 11.3 dB at 106 GHz with 3 dB bandwidth from 103 to 110 GHz. There are some obvious variations of the center frequency and gain between the simulation and measurement. The input small-signal of approximately -12 dBm in the $S$-parameters measurement might make the amplifier under a gain compression condition, which was confirmed by a subsequent power scanning test. The center frequency shifted up to higher frequency due to an inaccurate process as well as an inadequate simulation of uncommon coupling. Especially, the inter-digital coupling capacitor was so sensitive to technology process that the small signal performance differed markedly from the inaccurate technology process. In addition, the output impedance was situated around the edges of the Smith chart and, therefore, a slightly inaccurate process resulted in output mismatching, and eventually had a serious impact on the $S$-parameters of amplifier.

The measurements of the large-signal parameters require a consideration of the loss of connection components, including the probe and the waveguide. A full 2-port thru-reflect line (TRL) calibration was performed to define the reference planes to the probe tips before measuring the device. The input power of cascode amplifier was regulated to cover the linear and gain compressive region by adjusting the attenuation amount. The measured output power versus input power of amplifier at 106 GHz is shown in Fig. 9. The amplifier delivers a linear gain of 25.7 dB with a saturated output power of 0 dBm at room temperature. The amplifier compresses with input power larger than -25 dBm, which confirms that the input signal is not small enough to obtain a real linear gain in $S$-parameter measurements. The measured small-signal gain differs very little from the simulated one, unlike the center frequency. The relatively small output power may result from the comparatively short gate-width devices adopted to minimize the total drain current. Simultaneously, much more attention should be paid to the output power in the output matching design.

5. Conclusions

We have demonstrated a W-band high gain cascode amplifier based on a 0.15 $\mu$m gate-length InP-based HEMT process. The amplifier exhibits small-signal gain of 25.7 dB at 106 GHz with 0 dBm saturated output power. A lossy output matching network could be introduced to stabilize the output matching and flatten the gain response as well as decrease the sensitivity of output matching to the fabrication process. However, the successful design of a two-stage cascode amplifier demonstrates that InP HEMT technology has great potential for MMIC design at millimeter-wave frequencies.

Acknowledgement: The authors would like to acknowledge the assistance of Li Yankui and Ouyang Sihua for tuning the measurement equipment, and we also appreciate the help of all the members of the IMECAS compound semiconductor device department.