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J. Semicond. > 2013, Volume 34 > Issue 8 > 084001

SEMICONDUCTOR DEVICES

ANFIS-based approach to studying subthreshold behavior including the traps effect for nanoscale thin-film DG MOSFETs

T. Bentrcia1, F. Djeffal2, 3, and E. Chebaaki2

+ Author Affiliations

 Corresponding author: F. Djeffal, Email:faycal.djeffal@univ-batna.dz, faycaldzdz@hotmail.com

DOI: 10.1088/1674-4926/34/8/084001

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Abstract: A fuzzy framework based on an adaptive network fuzzy inference system (ANFIS) is proposed to evaluate the relative degradation of the basic subthreshold parameters due to hot-carrier effects for nanoscale thin-film double-gate (DG) MOSFETs. The effect of the channel length and thickness on the resulting degradation is addressed, and 2-D numerical simulations are used for the elaboration of the training database. Several membership function shapes are developed, and the best one in terms of accuracy is selected. The predicted results agree well with the 2-D numerical simulations and can be efficiently used to investigate the impact of the interface fixed charges and quantum confinement on nanoscale DG MOSFET subthreshold behavior. Therefore, the proposed ANFIS-based approach offers a simple and accurate technique to study nanoscale devices, including the hot-carrier and quantum effects.

Key words: hot-carrier degradationANFISfuzzy computationsubthresholdquantum effectsthin film

The double-gate metal oxide semiconductor field-effect transistor (DG MOSFET) architecture is considered as a promising device for nanoscale CMOS-based application. It has attracted the attention of a wide range of researchers, and this has led to many enhancements at both the design and practical implementation levels, where new materials and structural improvements have been adopted in order to obtain a higher efficiency performance[1-3].

However, even with all these efforts, many of the proposed improvements will be put into doubt if the severe constraints imposed by the current trends in downscaling and high packaging of electronics components are not treated appropriately[4]. In fact, by reducing the channel length of the device, its performance is affected, and such correlation is known as the short channel effect (SCE). The situation becomes worse when reaching the sub-100 nm technology node, where SCEs are aggressively amplified and various device characteristics are degraded considerably[5]. In addition, with the continuous scaling of the geometrical dimensions of MOSFET devices, their accurate modeling under various conditions of the working regime is becoming not only a critical domain, but also a necessary subject for understanding the miniaturization limits. The analytical modeling that has succeeded in some simple situations is in this case an intractable task due to the many mathematical and computational drawbacks encountered, especially when manipulating the joint Schrödinger/Poisson equation.

Another reliability drawback that is basically related to the reduction in the device dimensions is the formation of interface traps under the hot-carrier injection effect[6]. The hot-carrier-induced damage in MOSFET devices has two harmful consequences: trapping of carriers on the defect sites in the oxide region, and the creation of interface traps at the silicon-oxide interface[7]. As a result, the most obvious incident of this ageing phenomenon is that various parameters of the device become dependent on the duration of the work. For this reason, the carrier trapping in gate oxides is considered as the principal cause of instability for short channel MOSFETs, and has become one of the most important concerns for future MOS-integrated circuit development.

In order to have an accurate description of the DG MOSFET behavior with both an ultra thin silicon body and short channel length, the classical semiconductor equation should be extended to account for the quantum effects becoming dominant at the nanoscale level. The modeling framework based on quantum mechanics tools has received less interest due to the intractability or even the impossibility of getting a self-consistent solution from the Schrödinger/Poisson equations in terms of complexity and computational cost[8]. Hence, other alternative approaches have been used to study the immunity of DG MOSFETs based on the analysis of subthreshold or small signal parameters before and after stressing. Compact models are widely used for this purpose. These models are built from some simplifying assumptions that are required to reduce the complexity of the resolution approach without significantly altering the quality of the obtained results[9-12].

In this paper, we investigate the efficiency of an adaptive network-based fuzzy inference system (ANFIS) as a nanoscale thin-film DG MOSFET degradation behavior predictor in the subthreshold regime. This degradation is a complex phenomenon for thin-film MOSFETs, which mainly depends on the hot-carrier effect and quantum confinement. Two geometrical parameters were selected as the input variables to the fuzzy system (channel width and length) in order to predict the change in the subthreshold parameters: threshold voltage, drain-induced barrier lowering and OFF-current (Vth, DIBL and IOFF). In order to get an optimized structure, we tried several types of membership functions during the ANFIS training phase, so that the best one in terms of accuracy could be selected.

The remainder of this paper is organized as follows. In Section 2 we outline the hot-carrier degradation problem, in addition to some of the relevant literature. In Section 3 we present the main concepts relative to the ANFIS architecture and its hybrid learning algorithm. Section 4 depicts in detail the elaboration procedure of the numerical database and the configuration of various device parameters. The computational results are discussed in Section 5, and finally, we give an outlook on the main concluding remarks and future research axes in Section 6.

In response to the actual advances in semiconductor technology, besides the need for faster integrated circuits, the associated MOSFET sizes are continuously downscaled and therefore approaching their physical limits. On the other hand, an extreme difficulty is encountered when scaling some pertinent parameters, which is the case for the supply voltage used to operate these devices. This discrepancy in the velocity of downscaling geometrical and electrical parameters is the origin of a major reliability problem for short channel DG MOSFETs[13].

During the operation of the device, high electric fields are created in the silicon substrate near the drain-substrate junction due to the formation of a pinch-off region. The intensity of the electric fields increases rapidly with the reduction in the channel length, as predicted by Poisson's equation. When high drain voltages are applied, carriers in the channel and pinch-off regions reach non-equilibrium energy distributions. The energetic carriers qualified as hot carriers trigger various mechanisms at the silicon–oxide interface, and a fraction of the injected hot carriers lose their energy via interaction[14]. As the amount of injected hot carriers into the oxide depends strongly on the magnitude of the electric field inside the silicon substrate, good estimation of the hot-carrier degradation requires the accurate determination of the electric field distributions in silicon. Many of the approaches proposed for the modeling of hot-carrier distribution are based on the assumption of linear proportionality between the average carrier energy E and the local electric field Eloc

E=qlEloc,

(1)

where l is the free path of a carrier.

According to the above formula, the maximum energy gained by a carrier is at most equal to that of an elementary charge moving across the potential difference between the drain and source electrodes of the device. If this assertion is true, no carrier injection should take place when the drain–source voltage is below the potential barrier at the Si–SiO2 interface. However, significant substrate and gate currents are well detected at drain biases below this value, which constitutes a weak point for this model.

In order to remedy this paradoxical aspect, a more general framework should be used. Under the quantum theory of barrier penetration, carriers going across the local energy barrier at the Si–SiO2 interface are considered as particles incident upon a barrier potential. So for each carrier there are two probability measures: a probability of reflection and a probability of transmission[15]. Both probabilities are related to the opacity of the potential barrier, which depends in turn on many parameters such as the carrier energy. Thus, the carrier injection process is a complex function of the applied biases, the position along the channel, and the type of carrier being injected among other factors, which cannot be modelled analytically in short channel devices.

After the long working duration of a MOSFET device, a fraction of the injected carriers are trapped at defect sites in the oxide or at sites very close to the Si–SiO2 interface. Interfacially trapped holes that are positively charged have a high probability of being occupied by the electrons injected into the oxide. An amount of energy is released when the interfacially trapped hole is neutralized by electron capture, and such energy is sufficient to disrupt the chemical bonds near the interface to create an interface trap[16].

The damage generated by the hot-carrier effect is localized near the drain side since the electric field is maximal at this location. One way to look at this effect is to divide the MOSFET channel into two regions: the fresh region and the damaged region[17], which results in a threshold voltage that is larger than the fresh part of the channel. Thus, the general trend of a damaged device is that the threshold voltage increases and the drive current decreases as negative trapped-charge builds up or interface trap generation proceeds[18]. Based on analytical models, such an effect is more pronounced at large drain voltages for larger interface charge region lengths, and the device is severely affected by the presence of negative or positive traps. The threshold voltage near the drain end increases drastically due to the presence of negative interface charge density and reduces gradually for positive interface charge density[19].

It is common to characterize the device degradation by assessing the shifts before and after the device is stressed. Therefore, the relative variation in a device parameter can be used to estimate the hot-carrier-induced failure time, which indicates that the circuit may no longer function properly where separate equations including empirical constants are developed for gate voltage regions. For example, it is observed that the variation in threshold voltage with stressing time follows a power law[20] as

ΔVthVth0K1tn1,

(2)

where both fitting parameters K1 and n1 are dependent on the biasing applied voltages (Vds and Vgs).

In almost artificial intelligence-based models, the cornerstone of the elaborated approaches consists of the development of an interpolative input–output mapping, where an equivalent easy to use scheme is introduced with a set of configurable parameters to be adjusted so that a good match between the predicted and real outputs is obtained. In general, a training algorithm is used to minimize such discrepancy between both outputs. It is worth noting that there is no guarantee that the execution of such algorithms will lead to a global optimum, and therefore a validation phase for these models is a requirement.

The general structure of a fuzzy inference system includes transformations based on membership functions and a fuzzy extended version of the implication rule that maps the input characteristics to a single valued output[21]. In many cases, the type of membership functions and the rule structure is essentially predetermined by the user's interpretation of the characteristics of the variables in the model. However, in some situations, simply looking at the data cannot specify these aspects and the need for more robust strategies arises.

The ANFIS structure can be considered as a multilayer feed forward network, where neural network learning algorithms and fuzzy reasoning cooperate in the same framework to map nonlinear relationships within complex systems. In this formalism, the input space is divided into many local subregions, which means that several of them can be activated simultaneously by a single input, and then a simple local model given by a linear function is attached to each region[22]. The ability of ANFIS-based approaches to combine the advantages of the fuzzy computation with the numerical prediction provided by the neural networks has motivated their successful application in various engineering fields such as energy management, machining process and medical diagnosis[23-25].

In order to highlight the ANFIS architecture and function, we consider a system with two inputs identified in this work as the channel length and thickness, because they are the principal parameters and have a strong influence on the short channel and quantum effects. The number of fuzzy sets attached to each input is denoted by n and m, respectively. Hence, the total number of Takagi-Sugeno-Kang fuzzy IF–THEN rules is nm. The generic expression of such rules is given by

Rulek:IFLisAiandtsiisBjTHENfk=pkL+qktsi+rk,i=¯1,m,j=¯1,n,k=¯1,mn,

(3)

where Ai and Bj are the fuzzy sets associated with the geometrical input parameters, and pk, qk and rk are the linear parameters in the consequent part of the rule. The corresponding ANFIS architecture is composed of interconnected nodes organized in five functional layers as follows[26].

(1) Input nodes: each node of this layer deduces the membership grades of the crisp inputs based on the appropriate fuzzy sets using membership functions

{O1,s=μAi(L),s=¯1,m,O1,s=μBj(tsi),s=¯m+1,m+n.

(4)

If we assume that we have a generic membership function, then its representation can be given by the following expression

μ(x)=F(x;av,=,1,:,h),

(5)

where x is a generic variable denoting the channel length or thickness, and {av,=,1,:,h} indicates the parameters' set of the membership function in the premise part of the fuzzy rule that fixes the shape of the membership function.

(2) Rule nodes: nodes in this layer determine the fulfillment degree of the premise part of the rules by input values, using node functions as

O2,k=t(μAi(L),μBj(tsi))=μAi(L),μBj(tsi)=ωk,k=¯1,mn,

(6)

where t is a t-norm operator such as multiplication or minimum. The ωk output indicates the firing strength of the kth rule.

(3) Average nodes: the role of this third layer is to calculate the ratio of each rule's firing strength to the sum of all the rule's firing strength. So, ¯ωk is taken as the normalized firing strength

O3,k=¯ωk=ωkmnl=1ωl,k=¯1,mn.

(7)

(4) Consequent nodes: each node in this layer computes the normalized output of a rule for current outputs L and tsi based on the node function

O4,k=¯ωkfk=¯ωk(pkL+qktsi+rk),

(8)

where {pk, qk, rk} is the consequent parameter set of rule k.

(5) Output nodes: this layer contains only a single node that sums the outputs of the previous layer nodes to obtain the overall network output

O5,1=mnk=1¯ωkfk=mnk=1ωkfkmnk=1ωk.

(9)

The deposition of these layers is illustrated in Fig. 1.

Figure  1.  Illustrative representation of ANFIS with two input parameters and two MFs.

The least square error criterion is used to tune up the ANFIS architecture configuration and is given by

E=No=1Eo=No=1(Tofouto)2,

(10)

where Eo is the error measure for the Oth entry of the given training data set, To is the desired output of the Oth entry and fouto is the output of ANFIS using the Oth entry. If the premise parameters {av,=,1,:,h} are fixed, then the output of the whole system can be expressed as a linear combination of the consequent parameters {pk, qk, rk} as

f=Bθ,

(11)

where

f=[fout1foutN],

(12)

θ=[p1q1r1pmnqmnrmn],

(13)

B=[¯ω1L1¯ω1tsi1¯ω1¯ωmnL1¯ωmntsi1¯ωmn¯ω1L2¯ω1tsi2¯ω1¯ωmnL2¯ωmntsi2¯ωmn¯ω1LN¯ω1tsiN¯ω1¯ωmnLN¯ωmntsiN¯ωmn].

(14)

Since this equation is a standard linear least square problem, its algebraic solution (the estimator of the unknown matrix θ) can be written as[27]

θ=(BTB)1BTf,

(15)

where BT and B1 are the transpose and the inverse of matrix B, respectively.

The hybrid learning algorithm of the ANFIS combines the gradient method with the least square method to update the parameters, where a generic parameter α formed by the union of the premise and the consequent parameters is updated using the formula

Δα=ηEα,

(16)

with η a learning rate.

During the training phase, α is updated at each training epoch in a hybrid manner. More specifically, the consequent parameters of α are updated firstly using a least square algorithm, and the premise parameters are then adjusted by back propagating the errors. However, other alternative methods exist for these optimization processes in learning, such as the genetic algorithm (GA) and particle swarm optimization (PSO) based approaches, but the hybrid learning algorithm remains the most widely used in various applications[28, 29].

Since the accuracy of a properly trained ANFIS depends on the accuracy and the effective representation of the data used for its training, the database employed for this purpose should be carefully elaborated. The 3-D schematic cross-sectional view of the DG MOSFET device used in this work is depicted in Fig. 2, where an interfacial trap density is assumed to exist near the drain side as a result of the hot-carrier injection. In the elaboration procedure of the training database, different channel lengths and thicknesses are considered for evaluating the range of effects that may be more significant for analysis.

Figure  2.  3-D cross-sectional view of the symmetrical DG MOSGET including interface traps.

Various subthreshold characteristics (IOFF, Vth and DIBL) associated to a DG MOSFET structure with different channel lengths and thickness values are obtained numerically using the ATLAS 2-D device simulator[30]. A total of, 91 sets of data are selected by parsing the channel length range with a step of, 5 nm and the channel thickness range with a step of 0.5 nm. The set of geometrical and electrical parameters conserved during the running of all simulations is given in Table 1.

Table  1.  Device design and simulation parameters.
DownLoad: CSV  | Show Table

From the simulated device structure, it can be seen that the channel and the source/drain regions have uniform doping concentrations. All simulations are carried out using two carrier types, the drift–diffusion model without impact ionization, doping concentration-dependant carrier mobility and the electric field-dependant carrier model. SRH recombination/generation is also included in the simulation to account for the leakage currents.

In our work, the subthreshold behavior of the nanoscale DG MOSFET is based on the extraction of some pertinent parameters describing the function of the device. The threshold voltage expresses the gate voltage at which an inversion charge connecting the source/drain electrodes is established. Figure 3 compares the threshold voltage curves for fresh and damaged cases as obtained using numerical simulation. For both cases, the threshold voltage increases with the channel length to reach a constant value, which is the long channel threshold voltage value. As predicted, the damaged device has a higher threshold voltage because a higher applied gate voltage is needed to make the device turn on. Another interesting feature is related to the recorded results for very short channel lengths, where both curves become closer in this case. This can be explained by the strong correlation between the hot-carrier degradation and the short channel effect.

Figure  3.  Variation in threshold voltage DGMOSFET with and without traps as a function of channel length (tsi = 2 nm).

In Fig. 4, the variation in the threshold voltage as function of the channel width is presented with a fixed value of the channel length.

Figure  4.  Variation in threshold voltage DGMOSFET with and without traps as a function of channel width (L= 75 nm).

The drain-induced barrier lowering, which reduces the threshold voltage for an increase in drain voltage, is calculated from the difference between the threshold voltages at low and high values of the drain–source voltage, and these are equal to 0.1 and 0.3 V, respectively. As shown in Fig. 5, the DIBL effect is more pronounced for the short channel length devices with and without interface traps.

Figure  5.  Variation in DIBL DGMOSFET with and without traps as a function of channel length (tsi = 3 nm).

The OFF-current arises due to the fact that the DG MOSFET is not an ideal switch since there is still some leakage current that flows through it in the OFF-state. For nanoscale devices, both short channel and hot-carrier degradation effects can induce a remarkable change in such drain controllability in the subthreshold regime.

Figure 6 shows the variation in the subthreshold current as a function of the channel length. From this figure, it can be noted that the subthreshold current is pronounced for short channel lengths in both cases (fresh and damaged devices). Another remarkable feature that is clearly shown consists of the diminution of the subthreshold current when interface traps are considered, and this can be due to the trapping of a portion of carriers forming the subthreshold current in addition to the increase in the leakage current for nanoscale devices.

Figure  6.  Variation in subthreshold current DGMOSFET with and without traps as a function of channel length (tsi = 4 nm).

Since the performance of a well-trained ANFIS is strongly affected not only by the exhaustiveness of the training data on the considered interval but also by the type and number of MFs used to characterize the input variables, the training data set is obtained numerically using the 2-D Atlas simulator. The specification of the type and number of MFs is determined by the trial and error approach because no well-established method that can achieve this task optimally exists. So, the MFs are selected heuristically and verified empirically.

In this work, the number of MFs associated with the input variables is determined by exhaustively searching a fixed interval, and we find that the best results are located within the interval [2-15] × [2-15]. Thus, the number of fuzzy IF-THEN rules for ANFIS is bounded by the following interval [4-225]. The obtained results seem to suggest that using Gaussian combination, generalized bell-shaped and shaped MFs for the threshold voltage, the drain-induced barrier lowering and subthreshold current, respectively, give superior performance compared to other types of MFs. The analytical expressions of the three adopted MFs are indicated below.

The Gaussian combination-shaped MF is defined as

μ(x;σ1,σ2,c1,c2)=e(xc1)22σ21+e(xc2)22σ22.

(17)

Whereas the generalized bell-shaped MF is given by

μ(x;a,b,c)=11+|xca|2b,

(18)

and the shaped MF can be formulated as

μ(x;a,b,c,d)={0,xa,2(xaba)2,axa+b2,12(xbba)2,a+b2xb,12(xcdc)2,cxc+d2,2(xddc)2,c+d2xd,0,xd.

(19)

The best membership function configuration for the channel length and thickness in the case of the prediction of the threshold voltage relative degradation is illustrated in Figs. 7 and 8.

Figure  7.  Gaussian combination membership functions of the channel length input parameter in the case of threshold voltage degradation.
Figure  8.  Gaussian combination membership functions of the channel thickness input parameter in the case of threshold voltage degradation.

In order to show the obtained fuzzy rule responses, Figures 9, 10 and 11 depict the ANFIS controller rule surface for the variation in the relative degradation of the threshold voltage, drain-induced barrier lowering and subthreshold current, respectively, as a function of both channel length and thickness. Since the threshold voltage and the drain-induced barrier lowering are correlated, they present a similar behavior characterized by the presence of many local optima, which expresses the modeling complexity of both parameters in contrast to the subthreshold current, which presents a more shaped behavior. A similar situation has been deduced using analytical compact modeling for the case without introducing quantum effects, where the analytical models associated with the threshold voltage are more complicated and require more elaborate methods for their resolution compared to those associated with the subthreshold current[31-34].

Figure  9.  ANFIS controller rule surface for the threshold voltage relative degradation.
Figure  10.  ANFIS controller rule surface for the DIBL relative degradation
Figure  11.  ANFIS controller rule surface for the subthreshold current relative degradation.

Figures 12 and 13 represent the regression curves of the threshold voltage relative degradation for the training and testing phases. From these figures, it is easy to note that a positive correlation exists between the predicted and numerical values of the relative degradation in the case of the testing data set, which means that a sufficient agreement is satisfied between the predicted and numerical results.

Figure  12.  Regression curve of the threshold voltage relative degradation for the training data.
Figure  13.  Regression curve of the threshold voltage relative degradation for the testing data.

Figures 14 and 15 represent the regression curves of the drain-induced barrier lowering and the subthreshold current relative degradations for the testing phase. In Fig. 14, the correlation between the predicted and numerical values is negative in contrast to Fig. 15, which shows a positive correlation.

Figure  14.  Regression curve of the DIBL relative degradation for the testing data.
Figure  15.  Regression curve of the subthreshold current relative degradation for the testing data.

From these figures, it can be noticed that for different output variables, the elaborated fuzzy models were able to describe efficiently and with high accuracy, the general tendency behavior of the relative degradation in the threshold voltage, DIBL and subthreshold current. Hence, the adoption of fuzzy logic-based frameworks can be of crucial importance in dealing with nanoscale devices, especially with the inclusion of the parasitic effects occurring at this level and making the analytical modeling an intractable or even an impossible task to achieve.

A summary of the main obtained results for both phases (training and testing phases) is provided in Table 2 for different subthreshold behavior parameters.

Table  2.  Summary of the main obtained results.
DownLoad: CSV  | Show Table

As deduced from these results, the correlation coefficient (R) for the testing data is comprised of an absolute value between 0.7 and 0.9. Such a value indicates that we have a strong correlation between the predicted and the measured relative degradation values of the considered parameters' relative degradation. Thus, the performance of our proposed fuzzy approach is acceptable and can be used for further analysis of device behavior in nanoelectronic digital applications.

In this paper, an ANFIS-based approach has been proposed to efficiently estimate the relative degradation of the threshold voltage, drain-induced barrier lowering and the subthreshold current, which are considered the principal parameters that characterize CMOS-based devices in the subthreshold regime. Due to the strong influence of the channel length and thickness on the hot-carrier and quantum confinement effects, they were used as the input variables for the fuzzy system. Thanks to the numerical results obtained using the 2D-ATLAS simulator, it was possible to construct the required training database, where a hybrid learning algorithm was used to configure the different premises and consequent parameters included within the IF–THEN rules. The obtained performance demonstrated that the proposed approach can be implemented into circuit simulators in order to study nanoscale CMOS devices, including the hot-carrier degradation effects. The interesting features of the capabilities of ANFIS in dealing with the complexity and uncertainty related to the phenomenological description of device phenomena at a nanoscale level which are statistical in nature, make our proposed approach an adequate tool for future reliability prediction purposes. As a future work direction, the proposed framework can be extended by also including the small signal parameters, which affect the device behavior for analog circuit applications. However, new complex models and simulations should be developed in this case.



[1]
Kaur H, Kabra S, Haldar S, et al. An analytical drain current model for graded channel cylindrical/surrounding gate MOSFET. Microelectron J, 2007, 38:352 doi: 10.1016/j.mejo.2007.01.003
[2]
Amat E, Rodrìguez R, Nafrìa M, et al. Channel hot-carrier degradation under AC stress in short channel nMOS devices with high-k gate stacks. Microelectron Eng, 2009, 86:1908 doi: 10.1016/j.mee.2009.03.031
[3]
Ghosh P, Haldar S, Gupta R S, et al. An analytical drain current model for dual material engineered cylindrical/surrounded gate MOSFET. Microelectron J, 2012, 43:17 doi: 10.1016/j.mejo.2011.10.001
[4]
International Technology Roadmap for Semiconductors (ITRS), Published online at http://public.itrs.net, 2009
[5]
Difrenza R, Linares P, Ghibaudo G. The impact of short channel and quantum effects on the MOS transistor mismatch. Solid-State Electron, 2003, 47:1161 doi: 10.1016/S0038-1101(03)00033-9
[6]
Bentrcia T, Djeffal F. Compact modeling of multi-gate MOSFET including hot-carrier effects. CMOS Technology:Electrical Engineering Developments Series, Vol. 1. Chap. 4. New York:Nova Publishers, 2011
[7]
Pagey M P. Hot-carrier reliability simulation in aggressively scaled MOS transistors. PhD Dissertation, Electrical Engineering Department, Vanderbilt University, Nashville, Tennessee, USA, 2003 http://etd.library.vanderbilt.edu/available/etd-12032003-100902/unrestricted/Thesis.pdf
[8]
Prégaldiny F, Lallement C, Mathiot D. Accounting for quantum mechanical effects from accumulation to inversion, in a fully analytical surface-potential-based MOSFET model. Solid-State Electron, 2004, 48:781 doi: 10.1016/j.sse.2003.12.010
[9]
Ghoggali Z, Djeffal F, Lakhdar N. Analytical analysis of nanoscale double-gate MOSFETs including the hot-carrier degradation effects. Int J Electron, 2010, 97:119 doi: 10.1080/00207210902894746
[10]
Bendib T, Djeffal F. Electrical performance optimization of nanoscale double-gate MOSFETs using multi-objective genetic algorithms. IEEE Trans Electron Devices, 2011, 58:3743 doi: 10.1109/TED.2011.2163820
[11]
Bentrcia T, Djeffal F, Benhaya A. Continuous analytic Ⅳ model for GS DG MOSFETs including hot-carrier degradation effects. Journal of Semiconductors, 2012, 33:014001 doi: 10.1088/1674-4926/33/1/014001
[12]
Djeffal F, Bentrcia T, Abdi M A, et al. Drain current model for undoped gate stack double gate (GSDG) MOSFETs including the hot-carrier degradation effects. Microelectron Reliab, 2011, 51:550 doi: 10.1016/j.microrel.2010.10.002
[13]
Djeffal F, Bentrcia T, Bendib T. An analytical drain current model for undoped GSDG MOSFETs including interfacial hot-carrier effects. Phys Status Solidi C, 2011, 8:907 doi: 10.1002/pssc.201000158
[14]
Tyaginov S E, Starkov I A, Triebl O, et al. Interface traps density-of-states as a vital component for hot-carrier degradation modeling. Microelectron Reliab, 2010, 50:1267 doi: 10.1016/j.microrel.2010.07.030
[15]
Eisberg R, Renick R. Notes on modern physics. John Wiley and Sons, NY, 1969
[16]
Djeffal F, Bendib T, Abdi M A. A two-dimensional semi-analytical analysis of the subthreshold-swing behavior including free carriers and interfacial traps effects for nanoscale double-gate MOSFETs. Microelectron J, 2011, 42:1391 doi: 10.1016/j.mejo.2011.09.008
[17]
Ho C S, Huang K Y, Tang M, et al. An analytical threshold voltage model of NMOSFETs with hot-carrier induced interface charge effect. Microelectron Reliab, 2005, 45:1144 doi: 10.1016/j.microrel.2004.10.007
[18]
Mahapatra S, Parikh C D, Rao V R, et al. A Comprehensive study of hot-carrier induced interface and oxide trap distributions in MOSFET's using a novel charge pumping technique. IEEE Trans Electron Devices, 2000, 47:171 doi: 10.1109/16.817583
[19]
Singh A K. An analytical study of hot-carrier degradation effects in sub-micron MOS devices. The European Physical Journal Applied Physics, 2008, 42(2):87 doi: 10.1051/epjap:2008047
[20]
Naseh S, Deen M J, Chen C. Hot-carrier reliability of submicron nMOSFETs and integrated nMOS low noise amplifiers. Microelectron Reliab, 2006, 46:201 doi: 10.1016/j.microrel.2005.04.009
[21]
Zadeh L A. Outline of a new approach to the analysis of complex systems and decision processes. IEEE Trans Syst, Man, Cybernetics, 1973, 3:28 http://www.oalib.com/references/13118707
[22]
Jang J. ANFIS:adaptive-network-based fuzzy inference system. IEEE Trans Syst Man Cybernytics, 1993, 23:665 doi: 10.1109/21.256541
[23]
Lo S P. An adaptive-network based fuzzy inference system for prediction of work piece surface roughness in end milling. Journal of Materials Processing Technology, 2003, 142: 665
[24]
Ying L C, Pan M C. Using adaptive network based fuzzy inference system to forecast regional electricity loads. Energy Conversion and Management, 2008, 49:205 doi: 10.1016/j.enconman.2007.06.015
[25]
Akdemïr B, Günes S, Oran B, et al. Prediction of cardiac end-systolic and end-diastolic diameters in m-mode values using adaptive neural fuzzy inference system. Expert Systems with Applications, 2010, 37:5720 doi: 10.1016/j.eswa.2010.02.038
[26]
Singh M. Adaptive network-based fuzzy inference systems for sensorless control of PMSG based wind turbine with power quality improvement features. PhD Dissertation, University of Quebec, MONTREAL, 16 JULY 2010
[27]
Lawson C L, Hanson R J. Solving least squares problems. Englewood Cliffs, NJ: Prentice-Hall, 1974
[28]
Nariman-Zadeh N, Darvizeh A, Dadfarmai M H. Design of ANFIS networks using hybrid genetic and SVD methods for the modelling of explosive cutting process. Journal of Materials Processing Technology, 2004, 155:1415 doi: 10.1007/s12239-009-0020-6
[29]
Jiang H M, Kwong C K, Ip W H, et al. Modeling customer satisfaction for new product development using a PSO-based ANFIS approach. Applied Soft Computing, 2012, 12:726 doi: 10.1016/j.asoc.2011.10.020
[30]
Atlas User's Manual: Device Simulation Software, 2008
[31]
Djeffal F, Ghoggali Z, Dibi Z, et al. Analytical analysis of nanoscale multiple gate MOSFETs including effects of hot-carrier induced interface charges. Microelectron Reliab, 2009, 49:377 doi: 10.1016/j.microrel.2008.12.011
[32]
Bentrcia T, Djeffal F, Abdi M A, et al. An accurate two dimensional threshold voltage model for nanoscale GCGS DGMOSFET including traps effects. 3rd IEEE International Conference on Signals, Circuits and Systems, Djerba, Tunisia, 2009 doi: 10.1007/978-94-017-8832-8_25
[33]
Bentrcia T, Djeffal F, Arar D. An analytical two dimensional subthreshold current model for nanoscale GCGS DG MOSFET including interfacial traps effects. Rev Sci Technol, 2010, 1:103 doi: 10.1007%2Fs10825-010-0329-4.pdf
[34]
Djeffal F, Meguellati M, Benhaya A. A two-dimensional analytical analysis of subthreshold behavior to study the scaling capability of nanoscale graded channel gate stack DG MOSFETs. Physica E:Low-Dimensional Systems and Nanostructures, 2009, 41:1872 doi: 10.1016/j.physe.2009.08.002
Fig. 1.  Illustrative representation of ANFIS with two input parameters and two MFs.

Fig. 2.  3-D cross-sectional view of the symmetrical DG MOSGET including interface traps.

Fig. 3.  Variation in threshold voltage DGMOSFET with and without traps as a function of channel length (tsi = 2 nm).

Fig. 4.  Variation in threshold voltage DGMOSFET with and without traps as a function of channel width (L= 75 nm).

Fig. 5.  Variation in DIBL DGMOSFET with and without traps as a function of channel length (tsi = 3 nm).

Fig. 6.  Variation in subthreshold current DGMOSFET with and without traps as a function of channel length (tsi = 4 nm).

Fig. 7.  Gaussian combination membership functions of the channel length input parameter in the case of threshold voltage degradation.

Fig. 8.  Gaussian combination membership functions of the channel thickness input parameter in the case of threshold voltage degradation.

Fig. 9.  ANFIS controller rule surface for the threshold voltage relative degradation.

Fig. 10.  ANFIS controller rule surface for the DIBL relative degradation

Fig. 11.  ANFIS controller rule surface for the subthreshold current relative degradation.

Fig. 12.  Regression curve of the threshold voltage relative degradation for the training data.

Fig. 13.  Regression curve of the threshold voltage relative degradation for the testing data.

Fig. 14.  Regression curve of the DIBL relative degradation for the testing data.

Fig. 15.  Regression curve of the subthreshold current relative degradation for the testing data.

Table 1.   Device design and simulation parameters.

Table 2.   Summary of the main obtained results.

[1]
Kaur H, Kabra S, Haldar S, et al. An analytical drain current model for graded channel cylindrical/surrounding gate MOSFET. Microelectron J, 2007, 38:352 doi: 10.1016/j.mejo.2007.01.003
[2]
Amat E, Rodrìguez R, Nafrìa M, et al. Channel hot-carrier degradation under AC stress in short channel nMOS devices with high-k gate stacks. Microelectron Eng, 2009, 86:1908 doi: 10.1016/j.mee.2009.03.031
[3]
Ghosh P, Haldar S, Gupta R S, et al. An analytical drain current model for dual material engineered cylindrical/surrounded gate MOSFET. Microelectron J, 2012, 43:17 doi: 10.1016/j.mejo.2011.10.001
[4]
International Technology Roadmap for Semiconductors (ITRS), Published online at http://public.itrs.net, 2009
[5]
Difrenza R, Linares P, Ghibaudo G. The impact of short channel and quantum effects on the MOS transistor mismatch. Solid-State Electron, 2003, 47:1161 doi: 10.1016/S0038-1101(03)00033-9
[6]
Bentrcia T, Djeffal F. Compact modeling of multi-gate MOSFET including hot-carrier effects. CMOS Technology:Electrical Engineering Developments Series, Vol. 1. Chap. 4. New York:Nova Publishers, 2011
[7]
Pagey M P. Hot-carrier reliability simulation in aggressively scaled MOS transistors. PhD Dissertation, Electrical Engineering Department, Vanderbilt University, Nashville, Tennessee, USA, 2003 http://etd.library.vanderbilt.edu/available/etd-12032003-100902/unrestricted/Thesis.pdf
[8]
Prégaldiny F, Lallement C, Mathiot D. Accounting for quantum mechanical effects from accumulation to inversion, in a fully analytical surface-potential-based MOSFET model. Solid-State Electron, 2004, 48:781 doi: 10.1016/j.sse.2003.12.010
[9]
Ghoggali Z, Djeffal F, Lakhdar N. Analytical analysis of nanoscale double-gate MOSFETs including the hot-carrier degradation effects. Int J Electron, 2010, 97:119 doi: 10.1080/00207210902894746
[10]
Bendib T, Djeffal F. Electrical performance optimization of nanoscale double-gate MOSFETs using multi-objective genetic algorithms. IEEE Trans Electron Devices, 2011, 58:3743 doi: 10.1109/TED.2011.2163820
[11]
Bentrcia T, Djeffal F, Benhaya A. Continuous analytic Ⅳ model for GS DG MOSFETs including hot-carrier degradation effects. Journal of Semiconductors, 2012, 33:014001 doi: 10.1088/1674-4926/33/1/014001
[12]
Djeffal F, Bentrcia T, Abdi M A, et al. Drain current model for undoped gate stack double gate (GSDG) MOSFETs including the hot-carrier degradation effects. Microelectron Reliab, 2011, 51:550 doi: 10.1016/j.microrel.2010.10.002
[13]
Djeffal F, Bentrcia T, Bendib T. An analytical drain current model for undoped GSDG MOSFETs including interfacial hot-carrier effects. Phys Status Solidi C, 2011, 8:907 doi: 10.1002/pssc.201000158
[14]
Tyaginov S E, Starkov I A, Triebl O, et al. Interface traps density-of-states as a vital component for hot-carrier degradation modeling. Microelectron Reliab, 2010, 50:1267 doi: 10.1016/j.microrel.2010.07.030
[15]
Eisberg R, Renick R. Notes on modern physics. John Wiley and Sons, NY, 1969
[16]
Djeffal F, Bendib T, Abdi M A. A two-dimensional semi-analytical analysis of the subthreshold-swing behavior including free carriers and interfacial traps effects for nanoscale double-gate MOSFETs. Microelectron J, 2011, 42:1391 doi: 10.1016/j.mejo.2011.09.008
[17]
Ho C S, Huang K Y, Tang M, et al. An analytical threshold voltage model of NMOSFETs with hot-carrier induced interface charge effect. Microelectron Reliab, 2005, 45:1144 doi: 10.1016/j.microrel.2004.10.007
[18]
Mahapatra S, Parikh C D, Rao V R, et al. A Comprehensive study of hot-carrier induced interface and oxide trap distributions in MOSFET's using a novel charge pumping technique. IEEE Trans Electron Devices, 2000, 47:171 doi: 10.1109/16.817583
[19]
Singh A K. An analytical study of hot-carrier degradation effects in sub-micron MOS devices. The European Physical Journal Applied Physics, 2008, 42(2):87 doi: 10.1051/epjap:2008047
[20]
Naseh S, Deen M J, Chen C. Hot-carrier reliability of submicron nMOSFETs and integrated nMOS low noise amplifiers. Microelectron Reliab, 2006, 46:201 doi: 10.1016/j.microrel.2005.04.009
[21]
Zadeh L A. Outline of a new approach to the analysis of complex systems and decision processes. IEEE Trans Syst, Man, Cybernetics, 1973, 3:28 http://www.oalib.com/references/13118707
[22]
Jang J. ANFIS:adaptive-network-based fuzzy inference system. IEEE Trans Syst Man Cybernytics, 1993, 23:665 doi: 10.1109/21.256541
[23]
Lo S P. An adaptive-network based fuzzy inference system for prediction of work piece surface roughness in end milling. Journal of Materials Processing Technology, 2003, 142: 665
[24]
Ying L C, Pan M C. Using adaptive network based fuzzy inference system to forecast regional electricity loads. Energy Conversion and Management, 2008, 49:205 doi: 10.1016/j.enconman.2007.06.015
[25]
Akdemïr B, Günes S, Oran B, et al. Prediction of cardiac end-systolic and end-diastolic diameters in m-mode values using adaptive neural fuzzy inference system. Expert Systems with Applications, 2010, 37:5720 doi: 10.1016/j.eswa.2010.02.038
[26]
Singh M. Adaptive network-based fuzzy inference systems for sensorless control of PMSG based wind turbine with power quality improvement features. PhD Dissertation, University of Quebec, MONTREAL, 16 JULY 2010
[27]
Lawson C L, Hanson R J. Solving least squares problems. Englewood Cliffs, NJ: Prentice-Hall, 1974
[28]
Nariman-Zadeh N, Darvizeh A, Dadfarmai M H. Design of ANFIS networks using hybrid genetic and SVD methods for the modelling of explosive cutting process. Journal of Materials Processing Technology, 2004, 155:1415 doi: 10.1007/s12239-009-0020-6
[29]
Jiang H M, Kwong C K, Ip W H, et al. Modeling customer satisfaction for new product development using a PSO-based ANFIS approach. Applied Soft Computing, 2012, 12:726 doi: 10.1016/j.asoc.2011.10.020
[30]
Atlas User's Manual: Device Simulation Software, 2008
[31]
Djeffal F, Ghoggali Z, Dibi Z, et al. Analytical analysis of nanoscale multiple gate MOSFETs including effects of hot-carrier induced interface charges. Microelectron Reliab, 2009, 49:377 doi: 10.1016/j.microrel.2008.12.011
[32]
Bentrcia T, Djeffal F, Abdi M A, et al. An accurate two dimensional threshold voltage model for nanoscale GCGS DGMOSFET including traps effects. 3rd IEEE International Conference on Signals, Circuits and Systems, Djerba, Tunisia, 2009 doi: 10.1007/978-94-017-8832-8_25
[33]
Bentrcia T, Djeffal F, Arar D. An analytical two dimensional subthreshold current model for nanoscale GCGS DG MOSFET including interfacial traps effects. Rev Sci Technol, 2010, 1:103 doi: 10.1007%2Fs10825-010-0329-4.pdf
[34]
Djeffal F, Meguellati M, Benhaya A. A two-dimensional analytical analysis of subthreshold behavior to study the scaling capability of nanoscale graded channel gate stack DG MOSFETs. Physica E:Low-Dimensional Systems and Nanostructures, 2009, 41:1872 doi: 10.1016/j.physe.2009.08.002
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    T. Bentrcia, F. Djeffal, E. Chebaaki. ANFIS-based approach to studying subthreshold behavior including the traps effect for nanoscale thin-film DG MOSFETs[J]. Journal of Semiconductors, 2013, 34(8): 084001. doi: 10.1088/1674-4926/34/8/084001
    T. Bentrcia, F. Djeffal, E. Chebaaki. ANFIS-based approach to studying subthreshold behavior including the traps effect for nanoscale thin-film DG MOSFETs[J]. J. Semicond., 2013, 34(8): 084001. doi: 10.1088/1674-4926/34/8/084001.
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    Received: 11 January 2013 Revised: 10 February 2013 Online: Published: 01 August 2013

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      T. Bentrcia, F. Djeffal, E. Chebaaki. ANFIS-based approach to studying subthreshold behavior including the traps effect for nanoscale thin-film DG MOSFETs[J]. Journal of Semiconductors, 2013, 34(8): 084001. doi: 10.1088/1674-4926/34/8/084001 ****T. Bentrcia, F. Djeffal, E. Chebaaki. ANFIS-based approach to studying subthreshold behavior including the traps effect for nanoscale thin-film DG MOSFETs[J]. J. Semicond., 2013, 34(8): 084001. doi: 10.1088/1674-4926/34/8/084001.
      Citation:
      T. Bentrcia, F. Djeffal, E. Chebaaki. ANFIS-based approach to studying subthreshold behavior including the traps effect for nanoscale thin-film DG MOSFETs[J]. Journal of Semiconductors, 2013, 34(8): 084001. doi: 10.1088/1674-4926/34/8/084001 ****
      T. Bentrcia, F. Djeffal, E. Chebaaki. ANFIS-based approach to studying subthreshold behavior including the traps effect for nanoscale thin-film DG MOSFETs[J]. J. Semicond., 2013, 34(8): 084001. doi: 10.1088/1674-4926/34/8/084001.

      ANFIS-based approach to studying subthreshold behavior including the traps effect for nanoscale thin-film DG MOSFETs

      DOI: 10.1088/1674-4926/34/8/084001
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      • Corresponding author: F. Djeffal, Email:faycal.djeffal@univ-batna.dz, faycaldzdz@hotmail.com
      • Received Date: 2013-01-11
      • Revised Date: 2013-02-10
      • Published Date: 2013-08-01

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