1. Introduction

Recently, wake-up receivers (WuRx) have been widely employed for battery-powered applications such as wireless sensor networks (WSNs)^[1], wireless body area networks (WBANs)^[2], radio frequency identification systems (RFIDs)^[3] and even electronic toll collection systems (ETCs)^{[4, 5]}. For these applications, the real working time is typically very short and the idle duration power consumption generally dominates the battery life. Utilizing WuRx is an efficient energy-saving strategy that can greatly reduce the idle duration power. A whole WuRx consists of the RF front-end and the baseband circuit. The WuRx baseband circuit, which is responsible for amplification, filtering, analog to digital conversion and digital processing, is an important building block in WuRx.

In many works^[6-8], only amplitude detection is adopted in the baseband circuit. The circuit structure is simple, but it has little interference rejection ability and the risk of a high false wake-up rate. A false wake-up will enable the power hungry main blocks and definitely increase the power consumption of the systems. To reduce false wake-ups, a narrowband passive R-C band-pass filter (BPF) is implemented to remove interference^[2]. However, the insertion loss degrades the wake-up sensitivity. To overcome this challenge, a delay-based BPF was proposed in Ref. [5]. The BPF is implemented digitally, so the sensitivity is not deteriorated. However, the method used in Refs. [2, 5] cannot reject the interference sufficiently. Strong interference could still pass detection and then lead to false wake-up operations.

In many application backgrounds, the first priority of WuRx is high sensitivity. Thus an open loop amplifier is adopted at the first stage of the WuRx baseband circuit^{[9, 10]} to get high sensitivity. In ETC application, the sensitivity requirement is -40 dBm, which is easy to satisfy. But a strict requirement is imposed on the sensitivity robustness. Neither too high nor too low a sensitivity is desired^[11]. It is obvious that baseband circuits with an open-loop amplifier are not robust enough and not suitable for ETC application. Besides, the DC offset of the amplifier will degrade the sensitivity robustness dramatically. An effective dc offset cancellation technique is therefore greatly needed.

In this paper, besides the amplitude detection method, a digital frequency detection method is newly introduced to reject strong interference and reduce the false wake-up rate. By using this method, out-of-band interference can be rejected completely. The amplitude and frequency double-mode detection method assures a high wake-up accuracy and low false wake-up rate. To enhance the sensitivity robustness, an improved closed-loop band-pass filter (BPF) with robust gain is employed at the first stage of the baseband circuit. Furthermore, a new DC offset cancellation technique is proposed, which can further improve the robustness.

2. System analysis

Figure 1 shows a block diagram of a typical on-board-unit (OBU) in an ETC system. It includes the WuRx and main circuits. Normally, the OBU is in sleep mode. The main circuits are powered off, while the WuRx is working all the time.

The WuRx consists of an RF envelope detector and a baseband circuit. In the ETC system^[12], the wake-up signal is a continuous 14 kHz square wave modulated to 5.8 GHz by amplitude-shift-key (ASK) modulation. The wake-up signal is received by the WuRx when the OBU is passing a toll. It is firstly down-converted to baseband by the RF envelope detector. Then the down converted signal is processed and judged by the baseband circuit. When the baseband circuit confirms the wake-up signal, it will turn on the entire OBU.

Figure 2 shows the proposed architecture of a WuRx baseband circuit. It consists of two BPFs, a comparator, a frequency detector, a reference and a clock generator.

The input signal ($V_{\rm in})$ is firstly amplified and filtered by BPF1. Then the comparator will output a digital signal with the same frequency of input signal if the input signal is strong enough. Afterwards, the digital frequency detector detects the signal frequency. The BPF1 and comparator fulfill the amplitude detection, and the frequency detector fulfills the frequency detection. Only when the input signal is passing both the amplitude and frequency detection, can the baseband circuit output the confirmed signal. Thus the baseband circuit achieves a high wake-up accuracy, and the false wake-up rate is limited.

In Fig. 2, the static output voltage of BPF1 and BPF2 is equal to $V_{1}$ and $V_{2}$, respectively. When applying an input signal in BPF1 with enough magnitude, the dynamic output voltage of BPF1 will be above $V_{2}$. Then the output states of the comparator will be changed. The sensitivity of the wake-up circuit can be derived as:

$\begin{equation} \label{eq1} {\rm Sensitivity}=\frac{\left| {V_1-V_2} \right|}{\rm Gain}, \end{equation}$

(1)

where Gain represents the gain of the BPF1.

From Eq. (1), the gain and the threshold voltage $\left| {V_1-V_2} \right|$ are the two factors that affect the sensitivity. To achieve a robust sensitivity performance, techniques should be developed to make both the gain and the threshold robust.

In this work, BPF1 is implemented with a closed-loop structure, which makes the gain stable. BPF2, whose input node is connected to gnd, is a dummy of BPF1. The output dc offset voltage of BPF1 and BPF2 is nearly the same. After subtraction, the threshold voltage $\left| {V_1-V_2} \right|$ becomes independent of the DC offset, and thus has a high robustness. This is the main idea of the proposed dc offset cancellation technique, and the details will be discussed in the next section.

The reference circuit provides current and voltage reference (including $V_{\rm b1}$ and $V_{\rm b2})$ for the analog modules, and the clock generator provides clock signals for the frequency detector.

3. Circuit implementation and design techniques

3.1 Band-pass filter

In this paper, a closed-loop capacitive-feedback BPF is adopted in the first stage of the baseband circuit. Firstly, the in-band gain of the BPF is the ratio of two capacitors, which is the most stable in integrated circuits. Secondly, the BPF can accomplish band-pass filtering and amplification at the same time, and the overall power consumption is saved. Additionally, the structure blocks the DC signal from the pre-circuit, which rejects the DC offset from the input signal.

A conventional integrated BPF^[13] is shown in Fig. 3(a). The equivalent resistance $R_{\rm MOS}$ of the sub-threshold diode-connected PMOS is extremely large, at the quantity level of G$\Omega$. The in-band gain of the integrated capacitive feedback BPF can be expressed as:

$\begin{equation} \label{eq2} G({\rm j}\omega )=\frac{{\rm j}\omega C_1 R_{\rm MOS} }{{\rm j}\omega C_2 R_{\rm MOS} +1}\approx \frac{C_1 }{C_2 }. \end{equation}$

(2)

From Eq. (2), the gain of BPF is the ratio of two capacitors, which is the most PVT-insensitive in integrated circuits. However, due to the single direction diode-connected PMOS, the conventional structure has the disadvantages of asymmetrical output and a long settling time. This leads to decreased gain robustness and other non-ideal effects.

An improved BPF structure is proposed in Fig. 3(b). The parallel connection of two identically connected transistors makes the impedance equally seen from both sides of the PMOS resistors. This leads to better symmetrical performance and a lower settling time.

Figure 4 shows the comparison between the conventional and proposed BPF in terms of simulated transient responses. Figure 4(a) is the input signal, and Figures 4(b) and 4(c) are the output waveforms of the conventional structure and proposed structure, respectively. From Fig. 4(b), the output wave of the previous amplifier is asymmetric to the DC voltage, and the settling time is seven periods of the input signal. While in Fig. 4(c), the output waveform of the proposed BPF is symmetrical and the settling time is reduced to three periods.

3.2 DC offset cancellation

Besides the gain of the BPF, another factor which affects the wake-up sensitivity is the threshold voltage $\left| {V_1-V_2} \right|$, and the main non-ideal factor which leads to weak robustness of the threshold voltage is the output dc offset of BPF1.

Considering the output dc offset voltage, the static output voltage of the BPF1in Fig. 3(b) can be derived as:

$\begin{equation} \label{eq3} V_1=V_{\rm b1}+\Delta V_{\rm d}, \end{equation}$

(3)

where $V_1$ is the static output voltage of the BPF and $V_{\rm b1}$ represents the bias voltage of the BPF, as shown in Figs. 2 and 3. $\Delta V_{\rm d}$ is the output dc offset voltage of BPF1. From Eq. (3), Equation (1) can be rewritten as:

$\begin{equation} \label{eq4} {\rm Sensitivity}=\frac{\left| {(V_{\rm b1}-V_2)+\Delta V_{\rm d}} \right|}{\rm Gain}. \end{equation}$

(4)

To save power, the MOSFETs in the BPF1 operate in the sub-threshold region. However, the dc offset of the MOSFETs working in the sub-threshold region is much worse than the MOSFETs working in the saturation region. Additionally, the gain of BPF1 is high, which leads to a large output dc offset voltage. Sometimes, $\Delta V_{\rm d}$ is at the same quantity level of $V_{\rm b1}-V_2$, but the opposite sign. From Eq. (4), the sensitivity will change dramatically due to the dc offset voltage variation.

To solve the DC offset problem, a dummy of BPF1 (BPF2) is adopted, as shown in Fig. 5. The component sizes of BPF2 are the same as BPF1, so the dc offset voltages of $V_1$ and $V_2$ are nearly the same. Thus the sensitivity can be derived as:

$\begin{equation} \label{eq5} {\rm Sensitivity}=\frac{\left| {(V_{\rm b1}+\Delta V_{\rm d} )-(V_{\rm b2}+\Delta V_{\rm d} )} \right|}{\rm Gain}=\frac{\left| {V_{\rm b1}-V_{\rm b2}} \right|}{\rm Gain}. \end{equation}$

(5)

It can be seen from Eq. (5) that, by the proposed cancellation technique, the sensitivity will be independent of the BPF output DC offset voltage. $V_{\rm b1}$ and $V_{\rm b2}$ are fixed voltages generated by a $V_{\rm gs}/R$ reference generator, as shown in Fig. 6. Since $C_{3}$ in BPF2 doesn't affect the dc offset, the value of $C_{3}$ could be minimized to save area.

The input DC offset voltage of the comparator influences the sensitivity too. But the magnitude of the input dc offset voltage of the comparator is much smaller than the output DC offset voltage of the BPF. So the dc offset of the comparator has less impact on sensitivity. A symmetrical comparator with DC current source is adopted, as shown in Fig. 7. Besides the relatively low offset performance, the comparator has the merit of high gain, which makes the comparator give ideal digital output waves.

3.3 Frequency detector

The frequency detector is implemented in the digital domain. It consists of a divider by two, a counter, a judgment logic block and an output logic block, as shown in Fig. 8.

The input signal is firstly divided by two by the divider. The divided signal has a duty-cycle of 50% and can assure the accuracy of frequency detection. Then the counter counts during the high level of the divided signal. At the negative edge of the divided signal, the judgment logic block latches the output of the counter. The input signal frequency can be derived as:

$\begin{equation} \label{eq6} f_{\rm input} =\frac{f_{\rm Clk} }{N}, \end{equation}$

(6)

where $f_{\rm input}$ and $f_{\rm Clk}$ represent the frequency of input and the clock signal, respectively. $N$ represents the latched output number of the counter.

The clock frequency $f_{\rm Clk}$ is fixed, so the judgment logic block can judge the input signal frequency by judging $N$. If the input signal frequency is confirmed, it gives out a high level output. Then the output logic block will give the final output signal. The output signal could be continuous-wave or static-state, according to the needs of the OBU.

The transfer function of the frequency detector is shown in Fig. 9. The digital frequency detector acts as an ideal filter here. It has a smooth passing band, sharp transition band and infinite stop band attenuation. The passing band of the WuRx baseband circuit is decided by the frequency detector. Thus, by utilizing the frequency detector, the baseband circuit has a strong inference rejection ability and low false wake-up rate.

It can be easily derived that the precision of the frequency detector equals the period of the clock signal. Thus the clock frequency should be as high as possible while keeping reasonable power consumption. In this work, a relaxation oscillator^[14] is adopted as the clock generator, as shown in Fig. 10.

4. Measurement results

The proposed WuRx baseband circuit was fabricated in 0.18 $\mu$m TSMC 3.3 V CMOS technology. Besides the large number of 3.3 V MOSFETs, several 1.8 V NMOS (less than 10) are adopted. Figure 11 shows a micrograph of the fabricated circuit. The core chip size is 0.35 $\times$ 0.39 mm$^{2}$.

Measurement results show that the circuit works well under 3.3 V to as low as a 1.8 V power supply. Generally, the worst case happens when a circuit is powered by the lowest supply voltage. To illustrate the function and robustness of the proposed circuit, measurement results under the lowest supply voltage (1.8 V) are presented below.

In the static state, the wake-up circuit has a dc current consumption of only 1.4 $\mu$A. When applying an input signal with -30 dBm amplitude, the dynamic current is 2.9 $\mu$A.

The wake-up sensitivity was tested by applying a 14 kHz square wave signal at the input port. Measurement results show that the circuit achieves a wake-up sensitivity of -54.5 dBm (0.42 mV). The required sensitivity of the ETC system^[12] from the RF end is $-40$ dBm. The proposed baseband circuit gives a 14.5 dB conversion loss margin for the RF envelope detector, which is quiet enough.

The wake-up accuracy was tested by applying a signal with a different amplitude and frequency at the input. Only when the signal amplitude is higher than the sensitivity and the frequency is in the passing frequency range, does the circuit give out a confirmed wake-up signal. The output signal is a continuous square wave with a half frequency of input signal, as shown in Fig. 12.

Figure 13 shows the wake-up sensitivity versus input frequency of the proposed circuit. In the passing frequency range (7-62 kHz), the sensitivity changes from -55 to $-48$ dBm. When out of the passing frequency range, the sensitivity is infinite. A BPF-only baseband circuit cannot reject interferers as sufficiently due to its gradual frequency response. But thanks to the frequency detector, the baseband circuit has a sharp transition band and infinite stop-band attenuation. The out-of-band interference can be rejected completely, no matter how strong it is. Therefore, the proposed circuit can reduce false wake-up operation effectively.

Figure 14 shows the measured sensitivity and current consumption versus temperature from $-50$ to 100 ℃. The sensitivity value roughly decreases with temperature and varies $\pm$1.4 dBm over the 150 ℃ range. The DC current keeps at 1.4 $\mu$A from $-40$ to 60 ℃, which is the most common working temperature range, and the current variation over the whole 150 ℃ range is only 0.2 $\mu$A.

Figure 15 shows the measured sensitivity and current consumption versus supply voltage from 1.8 to 3.3 V. The sensitivity varies $\pm$ 0.95 dBm over a 1.5 V supply voltage variation. The current increases with temperature from 1.4 to 1.7 $\mu$A over the 1.5 V supply range.

To the authors' knowledge, no prior work on an ETC WuRx baseband circuit has been reported. An ETC WuRx is reported in Refs. [4, 5], but the performances of the baseband circuit are not given. So it is impossible to compare the proposed wake-up baseband circuit with previous works under the same ETC application background. Several previously reported baseband circuits of other application backgrounds, the ETC standard requirements^[12] and the proposed circuit are compared in Table 1.

5. Conclusion

This paper presents a fully integrated baseband circuit for wake-up receivers with double-mode detection and high sensitivity robustness. It consists of a band-pass filter, a comparator, a frequency detector, as well as an embedded reference and clock generator. By the introduction of frequency detection, the interference rejection ability is enhanced and false wake-ups can be reduced. The improved closed-loop BPF and dc offset cancellation technique ensures that the circuit achieves a high sensitivity robustness. The measured sensitivity is $-54.5$ dBm with only $\pm$0.95 dBm variation from a 1.8 to 3.3 V power supply, and the temperature variation of the sensitivity is $\pm$1.4 dBm from -50 to 100 ℃. The current consumption is 1.4 $\mu$A under a 1.8 V power supply and the area is 0.12 mm$^{2}$.