Fig. 1.
SAR ADC architecture.
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| Citation: |
Jun Ma, Yawei Guo, Yue Wu, Xu Cheng, Xiaoyang Zeng. A 1-V 10-bit 80-MS/s 1.6-mW SAR ADC in 65-nm GP CMOS[J]. Journal of Semiconductors, 2013, 34(8): 085014. doi: 10.1088/1674-4926/34/8/085014
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J Ma, Y W Guo, Y Wu, X Cheng, X Y Zeng. A 1-V 10-bit 80-MS/s 1.6-mW SAR ADC in 65-nm GP CMOS[J]. J. Semicond., 2013, 34(8): 085014. doi: 10.1088/1674-4926/34/8/085014.
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A 1-V 10-bit 80-MS/s 1.6-mW SAR ADC in 65-nm GP CMOS
DOI: 10.1088/1674-4926/34/8/085014
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Abstract
This paper presents a 10-bit 80-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) suitable for integration in a system on a chip (SoC). By using the top-plate-sample switching scheme and a split capacitive array structure, the total capacitance is dramatically reduced which leads to low power and high speed. Since the split structure makes the capacitive array highly sensitive to parasitic capacitance, a three-row layout method is applied to the layout design. To overcome the charge leakage in the nanometer process, a special input stage is proposed in the comparator. As 80 MS/s sampling rate for a 10-bit SAR ADC results in around 1 GHz logic control clock, and a tunable clock generator is implemented. The prototype was fabricated in 65 nm 1P9M (one-poly-nine-metal) GP (general purpose) CMOS technology. Measurement results show a peak signal-to-noise and distortion ratio (SINAD) of 48.3 dB and 1.6 mW total power consumption with a figure of merit (FOM) of 94.8 fJ/conversion-step. -
References
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