1. Introduction

Recent trends and emerging issues often turn to the features of miniaturization and portability, targeted toward battery-powered electronic devices. Many battery-operated applications such as tablet PCs, smart phones, and portable devices demand the energy efficient analog-to-digital converter (ADC) on a very tight power budget. By improving on the semiconductor processes, the chip area allows the ADC to be integrated into a large scale system-on-chip (SoC). In a tablet PC SoC design, state-of-charge estimation is based on battery voltage measurement with an ADC. Accordingly, in order to increase the battery's lifespan, every design in the SoC chip must work with the lowest possible power consumption and need less silicon area. The ADC inputs can be used for the external Li-Ion battery measurement in a wide range of very low power applications. Among the methods found in the available topologies, the SAR (successive approximation register) is well-known for its contribution to energy efficiency and sustainability. The SA algorithm is a very good candidate for low-power solution^{[1, 2]}, especially when used for slow input signals about 1 MHz with a resolution of 8 to 12 bits^{[3, 4]}. It is accompanied by a relatively small-area silicon, mostly due to its simple architecture^[5-7].

An SAR ADC mainly consists of a sample-and-hold (S/H) circuit, a comparator, a digital-to-analog converter (DAC) and digital SAR control logic. Based on a feedback loop, the SAR converter converges, to determine the final digital code for output by using an iterative process, comparing the value of a DAC (digital-to-analog converter) with a represent sampled value of the input signal, captured by the S/H circuitry. The cycles for conversion are followed by the binary-search algorithm. The conversion process begins when sampling the input signal and using a clock period per bit. Accordingly, the sampling rate is lower than the clock divided by an $N+$ 1 factor.

Because the charge-redistribution SAR ADC was proposed about 38 years ago^[8], it has been widely used in many applications. However, for the charge redistribution SAR ADCs, with increasing the resolution of the SAR ADC, the total passive elements in DACs will also grow exponentially. To reduce the overall cost of the circuit, a smaller capacitor footprint must be used. In this paper, a 10-bit SAR ADC is fabricated in 55-nm CMOS logic process. The proposed 10-bit segmented capacitive charge redistribution DACs is achieved by composing of 4-bit least significant bit (LSB) array and 6-bit most significant bit (MSB) array. The measurement results show that this proposed ADC achieves a high ENOB of 9.8726 and a very small active area of 0.0462 mm². The power budget is derived from the SoC specification of the overall architecture. The power consumption should be below 3 mW for a maximum clock rate at 12 MHz. It is very suitable for embedded multi-voltage supply SoC applications to measure the Li-ion battery's remaining capacity.

2. Proposed SAR ADC architecture

The proposed charge redistribution SAR ADC is shown in Fig. 1. It consists of a sample-and-hold (S & H) circuit, a summation node, a TIQ-based comparator, sixteen level shifters and a digital SAR control logic and a feedback 10-bit charge redistribution split-capacitor DACs. The analog input voltage is sampled by the S & H block. The TIQ-based comparator is used to compare the analog input with the DAC output. The output of the comparator block is used to control the SAR control logic. Based on the output of the comparator, the feedback loop of SAR control logic performs a 10-bit binary-search algorithm to determine the digital output code. Level-up shifters are used to convert the low voltage control signals to the higher voltage level analog circuit. The charge redistribution DAC is controlled by the SAR control logic and successively approximates the analog input. The split-capacitor DACs also act as the sampling capacitors. The ADC performs a binary-search algorithm that uses the digital logic circuitry to drive the improved split-capacitor array DAC bit by bit in a successive manner. Based on the result of the comparison at each clock cycle between the outputs of the S & H circuit and DAC feedback from array capacitances, the ADC converges on the final digital output value. After 12 clock cycles, the proposed ADC performs a complete conversion and the digital output is obtained.

2.1 Charge redistribution DAC structure

A conventional architecture of charge redistribution DAC is made of binary-weighted capacitors^[8]. Typical SAR structures apply huge DAC capacitive arrays which are usually the bottleneck of power and area in design. From the power consumption viewpoint, to sample a full-scale sine wave at the Nyquist frequency, a traditional capacitive array on average consumes power^[9]:

$ \begin{equation} P_{\rm in} =\frac{C_{\rm T} V_{\rm R}^2}{T_{\rm S}}, \end{equation} $

(1)

where $P_{\rm in}$ is the power drawn from the input, $C_{\rm T}$ is the total capacitance of the array, $V_{\rm R}$ is the reference voltage and $T_{\rm s}$ is the conversion period.

The average power drawn from the reference voltage generator for charge redistribution is^[9]:

$ \begin{equation} P_{\rm ref} =\frac{C_{\rm T} V_{\rm R}^2}{2T_{\rm S}}. \end{equation} $

(2)

In fact, n-bit resolution requires 2$^{n}$ unit capacitors. Consequently, capacitor area and power dispassion grow exponentially ($C_{\rm T}$ = 2$^{n}$$C_{0})$ with respect to the number of bits (n) which damage the superiority of SAR ADCs in terms of area, power and speed, especially in increasing the number of bits. To shrink the area of the ADC, the total capacitor must be decreased as much as possible.

The best way to save energy consumption and improve the speed is to reduce the total capacitance of the internal DACs. The scheme of a two-stage (5b-5b) split-capacitor DAC shown in Fig. 2 is to reduce area and power. The capacitor top plates connect to the common mode voltage $V_{\rm cm}$. The bridge capacitor $C_{\rm B}$ is used to separate the top plates of the MSB-side and LSB-side capacitor sub-arrays in DAC. The MSB capacitor of the proposed split-capacitor array is reduced from 2$^{9}$C to 2$^{4}$C when compared with a conventional binary-weighted capacitor array. Accordingly, the split-capacitor array is useful in the low power consumption and small die area. To have the total weight value of the LSB array equal to the weight value of the lowest bit in the MSB array, a bridge capacitor is connected with a fractional value (32/31) to unity capacitor^[10]. The maximum switched element in the array of the right side is 2$^{4}$C while the lowest one is C. The series of attenuation capacitance and the entire right array must equal the C.

$ \begin{equation} C=\frac{C_{\rm B} \times 2^5C}{C_{\rm B} +2^5C}, \end{equation} $

(3)

which yields the value of $C_{\rm B}$,

$ \begin{equation} C_{\rm B} =\frac{2^5}{2^5-1}C=\frac{32}{31}C. \end{equation} $

(4)

The total capacitance and power consumption of the bridge capacitor method are reduced significantly compared with the previous works. However, the fractional value bridge capacitor has poor matching with other capacitors. Moreover, parasitic capacitor mismatch at nodes X and Y makes the nonlinear errors of the LSB array and MSB array. It is difficult to realize a fractional value capacitor and this is the main limit for this method. A new method is presented for the calibration of the bridge capacitor which allows a variable capacitor to compensate for any mismatch^[11]. This makes the control signals more complex and results in more power consumption.

2.2 The proposed split-capacitor DAC structure

In this paper, an improved two-stage (6b-4b) split-capacitor DAC scheme with an integer bridge capacitor (2C) in Fig. 3 is proposed because the non-integer capacitor suffers from a larger mismatch problem in practical implementation. In the proposed DAC, the top plates of the differential capacitor arrays in the DAC are connected to the single-ended input of the comparator and the LSB-side capacitors connected through the bridge capacitor $C_{\rm B}$. The bottom plates can be switched between two DC reference voltages ($V_{\rm ref}+$, $V_{\rm ref}-$) as in the conventional design. $V_{\rm ref}+$ stands for the top reference voltage and the typical voltage range is between 2.4 V and 3.3 V. $V_{\rm ref-}$ stands for the bottom reference voltage and the typical range is between 0 and 0.4 V.

The input master clock (MCLK) defines the sampling phase. The internal sampling clocks such as Samp_clk, Samp_clka and Samp_clkb are generated by MCLK. The DAC samples the input signal and generates an error voltage between the input and current digital estimate. DO[9 : 0] is the output data bit stream where the DO9 is corresponding to the MSB and DO0 is corresponding to the LSB. Additionally, the clock management block and PWRDWN signal are used to implement the power down feature.

A classical 6b upper array and 4b lower array architecture require a value of 16/15C for the bridge capacitor $C_{\rm B}$. It is possible to adjust an integer value for $C_{\rm B}$, to 2C, simply by placing an integer dummy capacitor $C_{\rm F}$, i.e. 15C, in the lower array to compensate the mismatch of the bridge capacitor and to terminate the capacitor array. The bridge capacitor to compensate for mismatch in Fig. 3 has a smaller impact than that of Fig. 2. Moreover, parasitic capacitances at X and Y are subtracted from the parasitic capacitor ($C_{\rm F})$ connected to ground. In this way, not only the DAC linearity is improved, but the presence of $C_{\rm F}$ avoids losing charge if the input signal is higher than the reference voltage. Capacitors $C_{\rm G}$ restore the common-mode value by switching from the supply voltage to ground at the end of the sampling period. In the proposed split-capacitor DAC, parasitic compensation and capacitor matching problems are improved.

A data conversion is achieved by two operations. Firstly in the sampling phase, the bottom plates of all capacitors are connected to the input voltage $V_{\rm IN}$ via the switches. Secondly in the redistribution phase, the corresponding switch connects to the reference voltage ($V_{\rm ref}$+) and the top plates of all capacitors become floating. During the sampling phase when the sampling switch is on, the MSB is set to "1" while all other bits are "0" and thus the bottom plates of MSB capacitor are tied to $V_{\rm ref}$+ and the rest to $V_{\rm ref}$-. After disconnecting the sampling switch, the input signal already sampled on the sub-DAC capacitors and the MSB is determined to keep "1" or set back to "0". Then, the next MSB is set to "1" and this procedure is repeated until all N bits are found.

As shown in Fig. 3, the bottom plates except the $C_{\rm F}$ connect to $V_{\rm ref}$, and then the comparator compares the input voltages with internal reference voltages of top plates $V_{\rm Y}$ at node Y by propagation delay. The MSB is determined by the result of comparison. In the next bit phase, SAR logic connects the MSB switch to $V_{\rm ref}$ by the given result, and raises the next bit to $V_{\rm ref}$ again. The operations of remaining bits are executed in a proper sequence.

Capacitor DACs were realized by an MIM structure with the unit C of 90 fF. The total sampling capacitance $C_{\rm s}$ of the proposed architecture is composed of four parts:

$ \begin{equation} C_{\rm S} =C_{\rm MSB} + C_{\rm LSB} + C_{\rm B} + C_{\rm F} = 95C, \end{equation} $

(5)

where the total capacitance of a 6 bit binary-weighted MSB DAC is 63C, and the 4 bit binary-weighted LSB DAC is 15C.

2.3 TIQ-based comparator

The dominant power dissipation sources in a SAR ADC are the comparator and the switching of the capacitor array. Conventional comparator structures such as the differential amplifier type, dynamic, and the fully differential latch-type comparators have some problems in A/D designs. They can be generalized as^[12]: large transistor area for higher accuracy, DC bias requirement, charge injection errors, metastability errors, high power consumption and resistor or capacitor array requirement.

Compared with conventional comparator structures, the threshold inverter quantizer (TIQ), which is based on systematic transistor sizing of a CMOS inverter, is a good choice for low-power applications. As shown in Fig. 4(a), TIQ consists of two cascaded CMOS inverters. The first stage can change its threshold voltage by transistor sizing and therefore sets the quantization level^[13]. The second stage increases gain and inverts the logic level to make TIQ an internally set comparator. As a result, the TIQ doesn't need the resistor array and eliminates the static power consumption.

Figure 4(b) shows the voltage transfer curve (VTC). Approximately, threshold voltage can be expressed as^[14]:

$ \begin{equation} V_{\rm th} =\frac{V_{\rm tn} +\sqrt {\dfrac{\mu _{\rm p} (W/L)_{\rm p} }{\mu _{\rm n} (W/L)_{\rm n} }} (V_{\rm DD} -\left| {V_{\rm tp} } \right|)}{1+\sqrt {\dfrac{\mu _{\rm p} (W/L)_{\rm p} }{\mu _{\rm n} (W/L)_{\rm n} }} }, \end{equation} $

(6)

where $V_{\rm tn}$ and $V_{\rm tp}$ are the transistors threshold voltages, and $\mu _{\rm n}$ and $\mu _{\rm p}$ are the electron and hole mobility, respectively,

The above equations obviously show that changing the aspect ratio $W/L$ of the NMOS and PMOS results in different threshold voltages and thus realizes the quantization. During the design process, the channel length, L, is kept constant and the channel width, W, is changed because the performance is more subject to L. The two stages must be of exactly the same size to maintain the same DC threshold voltage and to keep the linearity in balance for the voltage rising and falling intervals of high frequency input signals.

2.4 Level shifter

In the proposed SAR ADC, the sampling switch and the sub-DAC are controlled by a digital SAR logic control circuit. Therefore, between the digital logic circuit with 1.0 V supply voltage and the analog circuit with 3.3 V supply voltage, level converters are needed to convert the logic levels in an efficient way. For digital and analog voltage level conversion purpose, the circuit proposed in Ref. [15] can be employed.

The level shifter using cross-coupled PMOS load is shown in Fig. 5. The operation principle of the level shifter is as follows: N3 and N4 are driven by out-of-phase and in-phase signals of input IN respectively, the cross-couple devices, P3 and P4 provide current sources for N3 and N4, and lock the logic status at node TRAN at the same time. When IN transits from logic low to high, N3 will turn off and N4 turns on, while node TRAN starts to discharge until it turns to logic low. This will turn on P3 so the gate voltage of P4 will turn high, then P4 switches off, and node TRAN is locked as logic low, therefore the output node OUT transits from logic low to high as well like input node IN. The similar interpretion works when IN goes to logic low from high. Note that transistors of P1 and P2 are controlled by the digital core voltage (VCCD) and transistors of P3, P4 and P5 are controlled by the analog voltage (VCCA).

The level shifter has been used to convert the logic levels between the SAR and the analog parts. In the entire ADC, sixteen level shifters have been used: ten for the 10-bit output signals and six for the input clock signal and digital control pin.

3. Experimental results

A 10-b 1-MS/s SAR ADC has been fabricated in a 55-nm single-poly 6-metal (1P6M) CMOS process with an MIM capacitor option. Figure 6 shows the partial chip layout and pinning of the SoC testchip, which include the proposed SAR ADC. The design considered pre-existing structures on common multi-supply SoC applications. We show one can utilize the ADC on a SoC to realize an effective converter for measuring the battery voltage. The standard digital I/O modules are used and some logic gates and an I/O pin are added for testing the SAR digital circuitry.

Figure 7 shows the layout of the proposed SAR ADC IP. The complete prototype SAR ADC active area is 0.0462 mm² (138.85 × 332.8 $\mu $m²). A common-centroid symmetry layout is implemented to the capacitor array to reduce sensitivity to the capacitor mismatch problem and tolerate process variations^[16]. Dummy capacitor rings around the core capacitor array ensures that all unit capacitors in the core array have exactly the same structures and parasitic capacitance on each side in order to cancel out any systematic matching error^[17]. Careful matching in analog layout is to avoid linearity degradation and rearranges the layout recursively along with post-layout simulation.

The computer-aided ADC characterization method is based on the code density test and spectral analysis using the fast Fourier transform (FFT). Ramp-wave histogram test and sine-wave for FFT test of an ADC involve collecting a large number of digitized samples over a period of time in order to build a model of the converter's response to a specific, well-defined input signal. The complete system setup is shown in Fig. 8. In the testing set-up, Agilent E3648A provides the power supply and reference voltages, while two Tektronix AWG420 provide the clock signal and input signal, and a Keithley 6485 picometer measures current. Total power dissipation is 2.5 mW at 1 MSps conversion speed with 0.76 mA at 3.3 V analog supply and a 10 $\mu $A at 1.0 V digital supply.

The maximum input capacitance of the first cycle is 12 pF in the sampling mode. By using the equivalent circuit of the proposed ADC, as shown in Fig. 9, $R_{\rm IN}$ is the input resistor of SAR ADC during the sampling period. $C_{\rm IN}$ is the sampling capacitor of ADC. The relational expression of the sampling time ($T_{\rm samp})$ and the output impedance ($R_{\rm EXT})$ of the analog signal source can be written as Eq. (9).

$ \begin{equation} R_{\rm EXT} =\frac{T_{\rm samp} -20 \, {\rm ns}}{7 C_{\rm IN} }-R_{\rm IN} . \end{equation} $

(7)

$R_{\rm EXT}$ can only be determined by using the above equation. The output impedance ($R_{\rm EXT})$ of the analog signal source must satisfy the following expression when the MCLK frequency is 12 MHz (83.3 ns) and the clock is provided in the chip internally.

The static performance of differential nonlinearity (DNL) and integral nonlinearity (INL) of the proposed SAR ADC are reported in Fig. 10. The peak DNL (upper plot) at 1 MS/s is measured in the range of +0.4/-0.3 LSB while the INL (lower plot) at 1 MS/s is within +0.9/-0.2 LSB. The DNL and INL results show that there is no missing code in our work. Figure 11 shows the ADC dynamic performance (8192-point output FFT spectrum) at near Nyquist input with respect to a full-scale 10-kHz input sine wave signal. The plot shows apparent harmonics and elevated noise floor. When the sampling frequency is 1 MHz, the spectra for an input full-scale sine wave at 200 kHz is shown in Fig. 12, for which the SNDR of 61.1929 dB (ENOB = 9.8726) is achieved and the measured SNR, THD and SFDR are 64.496 dB, $-63.9289$ dB and 65.6917 dB, respectively. Figure 13 shows the SNR, SNDR and SFDR of the proposed ADC against the input signal frequency varies from 1 to 200 kHz, respectively.

Table 1 shows the performance summary of the proposed ADC. The parasitic capacitance can be reduced by using additional layers to form metal-insulator-metal (MIM) capacitors^[18]. The effective numbers of bits (ENOB) is 9.58 bits at the input frequency of 200-kHz as follows:

$ \begin{equation} {\rm ENOB}=\frac{\rm SNDR(dB)-1.76}{6.02}. \end{equation} $

(8)

We can compare the power efficiency parameter, FOM, of our proposed compressed sensing acquisition system to the conventional Nyquist sampling method by:

$ \begin{equation} {\rm FOM}=\frac{\rm Power}{2^{\rm ENOB}\times \min (f_{\rm s}, \, 2\times {\rm BW})}, \end{equation} $

(9)

where the $f_{\rm s}$ is sampling rate and the BW is the effective resolution bandwidth. The BW is over Nyquist frequency (0.5$f_{\rm s})$ from the experiment results. It indicates that our proposed ADC achieves an effective FOM of 3266 fJ/conversion-step.

Table 2 shows the performance comparison between our work and previous reported SAR ADCs with similar resolution and sampling rate^{[16, 17, 19-21]}. Despite the FOM for the proposed ADC being larger than previous works, the active die area is relatively small along with the highest ENOB of 9.8726 bits.

4. Conclusion

In this paper, a CMOS 1 MSps 10 b charge-redistribution SAR ADC with a capacitor reduction technique has been presented. The built-in TIQ-based comparator has no static power consumption which is suitable for the low power design. Built-in level shifters aimed at ultra low core voltage are designed using a 55 nm CMOS process. Experimental results of the proposed ADC show advantages over a conventional SAR ADC in accuracy and area. The ADC with an improved split-capacitor array DAC achieves 9.8726 ENOB up to the 200-kHz input signal while consuming only 2.5 mW at the maximum conversion rate 1 MS/s and occupying only 0.0462 mm² of the active area. The ADC gives only 12 clock cycles to perform a complete conversion. It is well applied when embedded into multi-supply voltage SoC designs to measure the voltage level on the battery.