A high voltage Bi-CMOS compatible buffer super-junction LDMOS with an N-type buried layer

Wei Wu; Bo Zhang; Jian Fang; Xiaorong Luo; Zhaoji Li

doi:10.1088/1674-4926/35/1/014009

J. Semicond. > 2014, Volume 35 > Issue 1 > 014009

SEMICONDUCTOR DEVICES

A high voltage Bi-CMOS compatible buffer super-junction LDMOS with an N-type buried layer

Wei Wu, Bo Zhang, Jian Fang, Xiaorong Luo and Zhaoji Li

+ Author Affiliations

Corresponding author: Wu Wei, Email:wuweiwwu@163.com

DOI: 10.1088/1674-4926/35/1/014009

Abstract: A novel buffer super-junction (SJ) lateral double-diffused MOSFET (LDMOS) with an N-type buried layer (NB) is proposed. An N^- buffer layer is implemented under the SJ region and an N-type layer is buried in the P substrate. Firstly, the new electric field peak introduced by the p-n junction of the P substrate and the N-type buried layer modulates the surface electric field distribution. Secondly, the N^- buffer layer suppresses the substrate assisted depletion effect. Both of them improve the breakdown voltage (BV). Finally, because of the shallow depth of the SJ region, the NB buffer SJ-LDMOS is compatible with Bi-CMOS technology. Simulation results indicate that the average value of the surface lateral electric field strength of the NB buffer SJ-LDMOS reaches 23 V/μm at 15 μm drift length which results in a BV of 350 V and a specific on-resistance of 21 mΩ · cm².

Key words: N-type buried layer, breakdown voltage, electric field modulation, lateral double-diffusion MOSFET, super-junction

References

[1]	Chen X B, Mawby P A, Salama T. Theory of a novel voltage-sustaining layer for power devices. J Microelectron, 1998, 29(12):1005 doi: 10.1016/S0026-2692(98)00065-2
[2]	Chen X B, Wang X, Sin J K O. A novel high-voltage sustaining structure with buried oppositely doped regions. IEEE Trans Electron Devices, 2000, 47(6):1280 doi: 10.1109/16.842974
[3]	Udrea F, Popescu A, Miline W I. A new class of lateral power devices for HVIC's based on the 3D RESURF concept. IEEE BTCM, 1998:187 http://ieeexplore.ieee.org/document/741921/?arnumber=741921
[4]	Udrea F, Popescu A, Miline W I. The 3D RESURF double-gate MOSFET:a revolutionary power device concept. Electron Lett, 1998, 34(8):808 doi: 10.1049/el:19980504
[5]	Wu W, Zhang B, Fang J, et al. High-voltage super-junction lateral double-diffused metal oxide semiconductor with a partial lightly doped pillar. Chin Phys B, 2013, 22(6):068501 doi: 10.1088/1674-1056/22/6/068501
[6]	Nassif-Khalil S G, Ander C, Salama T. Super-junction LDMOST on a silicon-on-sapphire substrate. IEEE Trans Electron Devices, 2003, 50(5):1385 doi: 10.1109/TED^2003.813460
[7]	Zhang B, Wang W, Chen W J, et al. High-voltage LDMOS with charge-balanced surface low on-resistance path layer. IEEE Electron Device Lett, 2009, 30(8):849 doi: 10.1109/LED^2009^2023541
[8]	Park I Y, Salama T. New superjunction LDMOST with n-buffer layer. IEEE Trans Electron Devices, 2006, 53(8):1909 doi: 10.1109/TED^2006.877007
[9]	Duan B X, Yang Y T, Zhang B. New superjunction LDMOS with N-type charges' compensation layer. IEEE Electron Device Lett, 2009, 30(3):305 doi: 10.1109/LED^2009^2012396
[10]	Onishi Y, Wang H, Xu E, et al. SJ-FINFET:a new low voltage lateral superjunction MOSFET. Proc IEEE ISPSD, 2008:111 http://ieeexplore.ieee.org/document/4538910/keywords
[11]	Rub M, Bar M, Deml G, et al. A 600 V 8.7Ω·mm² lateral super-junction transistor Proc IEEE ISPSD, 2006:305
[12]	Chen W J, Zhang B, Li Z J. Optimization of super-junction SOI-LDMOS with a step doping surface-implanted layer. Semicond Sci Technol, 2007, 22(5):464 doi: 10.1088/0268-1242/22/5/002
[13]	Wang W L, Zhang B, Li Z J. Super junction LDMOS with enhanced dielectric layer electric field for high breakdown voltage. Journal of Semiconductors, 2011, 32(2):262 http://www.jos.ac.cn/bdtxbcn/ch/reader/view_abstract.aspx?file_no=10080905&flag=1
[14]	Udrea F. State-of-the-art technologies and devices for high-voltage integrated circuits. IET Circuits Devices Syst, 2007, 1(5):357 doi: 10.1049/iet-cds:20070025
[15]	TCAD Sentaurus Manuals 2010 Version D-2010. 03

Fig. 1. Three-dimensional (3D) view of the NB buffer SJ-LDMOS.

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Fig. 3. Process flows of manufacture of the buried SJ layer. (a) Formation of N-buried layer. (b) Epitaxial growth and ions implantation to form N-buffer layer. (c) Gate oxide growth. (d) Ion implantation to form the SJ region.

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Fig. 4. The 3D equipotential contours for (a) the NB buffer SJ-LDMOS (350 V), (b) the buffer SJ-LDMOS (280 V), and (c) the conventional SJ-LDMOS (130 V) (12 V/contour. NB buffer SJ-LDMOS: $L_{\rm b}$ $=$ 5 $\mu$m, $D_{\rm d}$ $=$ 7 $\times$ 10$^{11}$ cm$^{-2}$, $D_{\rm b}$ $=$ 2.7 $\times$ 10$^{12}$ cm$^{-2}$; buffer SJ-LDMOS: $D_{\rm d}$ $=$ 1.6 $\times$ 10$^{12}$ cm$^{-2}$, $t_{\rm SJ}$ $=$ 1 $\mu$m, $t_{\rm d}$ $=$ 3.5 $\mu $m).

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Fig. 2. Cross-section of the NB buffer SJ-LDMOS.

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Fig. 5. (a) Lateral electronic field distributions, (b) vertical electronic field distributions and the charge density around the drain ($x=$ 25 $\mu$m) for the NB buffer SJ-LDMOS (350 V), buffer SJ-LDMOS (280 V), and the conventional SJ-LDMOS (130 V) at breakdown (NB buffer SJ-LDMOS: $L_{\rm b}$ $=$ 5 $\mu$m, $D_{\rm d}$ $=$ 7 $\times$ 10$^{11}$ cm$^{-2}$, $D_{\rm b}$ $=$ 2.7 $\times$ 10$^{12}$ cm$^{-2}$; Buffer SJ-LDMOS: $D_{\rm d}$ $=$ 1.6 $\times$ 10$^{12}$ cm$^{-2}$, $t_{\rm SJ}$ $=$ 1 $\mu$m, $t_{\rm d}$ $=$ 4.5 $\mu$m).

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Fig. 6. (a) BV versus $L_{\rm b}$ and $D_{\rm t}$ ($D_{\rm N}=D_{\rm P}$ $=$ 2 $\times$ 10$^{12}$ cm$^{-2})$. (b) BV and $R_{\rm on, sp}$ versus $D_{\rm b}$ ($L_{\rm b}$ $=$ 5 $\mu$m, $D_{\rm t}$ $=$ 1.6 $\times$ 10$^{12}$ cm$^{-2}$, $D_{\rm N}=D_{\rm P}$ $=$ 2 $\times$ 10$^{12}$ cm$^{-2})$. (c) BV as a function of charge imbalance in the N pillars of the SJ region. ($D_{\rm P}$ $=$ 2 $\times$ 10$^{12}$ cm$^{-2}$, $L_{\rm b}$ $=$ 5 $\mu$m, $D_{\rm d}$ $=$ 7 $\times$ 10$^{11}$ cm$^{-2}$, $D_{\rm b}$ $=$ 2.7 $\times$ 10$^{12}$ cm$^{-2}$.)

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Fig. 7. Dependences of BV and $R_{\rm on, sp}$ on $L_{\rm D}$ for an NB buffer SJ-LDMOS, a buffer SJ-LDMOS, and a conventional SJ-LDMOS.

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Table 1. FOM versus $L_{\rm D}$.

[1]	Chen X B, Mawby P A, Salama T. Theory of a novel voltage-sustaining layer for power devices. J Microelectron, 1998, 29(12):1005 doi: 10.1016/S0026-2692(98)00065-2
[2]	Chen X B, Wang X, Sin J K O. A novel high-voltage sustaining structure with buried oppositely doped regions. IEEE Trans Electron Devices, 2000, 47(6):1280 doi: 10.1109/16.842974
[3]	Udrea F, Popescu A, Miline W I. A new class of lateral power devices for HVIC's based on the 3D RESURF concept. IEEE BTCM, 1998:187 http://ieeexplore.ieee.org/document/741921/?arnumber=741921
[4]	Udrea F, Popescu A, Miline W I. The 3D RESURF double-gate MOSFET:a revolutionary power device concept. Electron Lett, 1998, 34(8):808 doi: 10.1049/el:19980504
[5]	Wu W, Zhang B, Fang J, et al. High-voltage super-junction lateral double-diffused metal oxide semiconductor with a partial lightly doped pillar. Chin Phys B, 2013, 22(6):068501 doi: 10.1088/1674-1056/22/6/068501
[6]	Nassif-Khalil S G, Ander C, Salama T. Super-junction LDMOST on a silicon-on-sapphire substrate. IEEE Trans Electron Devices, 2003, 50(5):1385 doi: 10.1109/TED^2003.813460
[7]	Zhang B, Wang W, Chen W J, et al. High-voltage LDMOS with charge-balanced surface low on-resistance path layer. IEEE Electron Device Lett, 2009, 30(8):849 doi: 10.1109/LED^2009^2023541
[8]	Park I Y, Salama T. New superjunction LDMOST with n-buffer layer. IEEE Trans Electron Devices, 2006, 53(8):1909 doi: 10.1109/TED^2006.877007
[9]	Duan B X, Yang Y T, Zhang B. New superjunction LDMOS with N-type charges' compensation layer. IEEE Electron Device Lett, 2009, 30(3):305 doi: 10.1109/LED^2009^2012396
[10]	Onishi Y, Wang H, Xu E, et al. SJ-FINFET:a new low voltage lateral superjunction MOSFET. Proc IEEE ISPSD, 2008:111 http://ieeexplore.ieee.org/document/4538910/keywords
[11]	Rub M, Bar M, Deml G, et al. A 600 V 8.7Ω·mm² lateral super-junction transistor Proc IEEE ISPSD, 2006:305
[12]	Chen W J, Zhang B, Li Z J. Optimization of super-junction SOI-LDMOS with a step doping surface-implanted layer. Semicond Sci Technol, 2007, 22(5):464 doi: 10.1088/0268-1242/22/5/002
[13]	Wang W L, Zhang B, Li Z J. Super junction LDMOS with enhanced dielectric layer electric field for high breakdown voltage. Journal of Semiconductors, 2011, 32(2):262 http://www.jos.ac.cn/bdtxbcn/ch/reader/view_abstract.aspx?file_no=10080905&flag=1
[14]	Udrea F. State-of-the-art technologies and devices for high-voltage integrated circuits. IET Circuits Devices Syst, 2007, 1(5):357 doi: 10.1049/iet-cds:20070025
[15]	TCAD Sentaurus Manuals 2010 Version D-2010. 03

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Received: 24 June 2013 Revised: 07 September 2013 Online: Published: 01 January 2014

A novel buffer super-junction (SJ) lateral double-diffused MOSFET (LDMOS) with an N-type buried layer (NB) is proposed. An N^- buffer layer is implemented under the SJ region and an N-type layer is buried in the P substrate. Firstly, the new electric field peak introduced by the p-n junction of the P substrate and the N-type buried layer modulates the surface electric field distribution. Secondly, the N^- buffer layer suppresses the substrate assisted depletion effect. Both of them improve the breakdown voltage (BV). Finally, because of the shallow depth of the SJ region, the NB buffer SJ-LDMOS is compatible with Bi-CMOS technology. Simulation results indicate that the average value of the surface lateral electric field strength of the NB buffer SJ-LDMOS reaches 23 V/μm at 15 μm drift length which results in a BV of 350 V and a specific on-resistance of 21 mΩ · cm².

A high voltage Bi-CMOS compatible buffer super-junction LDMOS with an N-type buried layer

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