1. Introduction

Lateral double-diffusion MOSFETs (LDMOS) act as an important component in power electronics applications for its facility integration. One of the main issues is the trade-off between breakdown voltage (BV) capability and specific on-resistance ($R_{\rm on, sp})$. The super-junction (SJ) concept^[1,2] used in LDMOS^[3,4] further improves the trade-off between BV and $R_{\rm on, sp}$. Unfortunately, the N pillars of the conventional SJ-LDMOST are depleted by neighboring P pillars as well as by the P substrate, while the P pillars are depleted by neighboring N pillars only, which is called the substrate-assisted depletion (SAD) effect. This effect causes a charge imbalance and results in the decrease of the BV. To alleviate the SAD effect, several new structures have been developed^[5-13]. In particular, with the development of the smart power integrated circuit (SPIC), it is very crucial to design an SJ-LDMOS integrated in SPICs implementing in a CMOS-compatible process^[14].

In this letter, we propose a buffer SJ-LDMOS with an N-type buried (NB) layer. The N$^{-}$ buffer layer suppresses the SAD effect and a more uniform surface electric field distribution is obtained due to the electric field modulation effect produced by an additional electric field peak between the P substrate and N-buried layer. The higher BV can be therefore achieved. In addition, this device is compatible with Bi-CMOS technology which can be facilely integrated in SPICs.

2. Device structure and mechanism

The NB buffer SJ-LDMOS is illustrated in Fig. 1. An N$^{-}$ buffer layer is implemented under the SJ region and an N-type layer is embedded in the P substrate. Firstly, the N$^{-}$ buffer layer compensates the lack of charge in the N pillars caused by the depletion between the N pillars and P substrate. The N$^{-}$ buffer layer therefore ensures the charge balance and suppresses the SAD effect. It also enables the NB buffer SJ-LDMOS to use shallow SJ pillars. Secondly, since the N-type layer is buried in the P substrate, a new electric field peak occurs at the p-n junction of the P substrate and the N-buried layer (i.e. D$_{1}$ junction in Fig. 1). This new electric field peak modulates the electric field distribution which causes a more uniform distribution of the surface electric field. It results in an improvement in BV. $t_{\rm SJ}$, $t_{\rm d}$, and $t_{\rm b}$ are the thickness of SJ region, N$^{-}$ buffer layer, and N-buried layer, respectively. $W_{\rm N}$ and $W_{\rm P}$ are the width of the N pillar and the P pillar. $L_{\rm ch}$ and $L_{\rm D}$ are the length of the channel and the drift length. $D_{\rm N}$, $D_{\rm P}$, $D_{\rm d}$, and $D_{\rm b}$ are the implantation doses of the N pillar, the P pillar, the N-buffer layer, and the N-buried layer, respectively. In this brief, $t_{\rm SJ}$ $=$ 1 $\mu$m, $t_{\rm d}$ $=$ $t_{\rm b}$ $=$ 4.5 $\mu$m, $h$ $=$ 9 $\mu$m, $W_{\rm N}=W_{\rm P}$ $=$ 1 $\mu$m, $L_{\rm ch}$ $=$ 5 $\mu$m, $L_{\rm D}$ $=$ 15 $\mu$m and $\rho_{\rm s}$ $=$ 65 $\Omega$$\cdot$cm are used, and $D_{\rm N}=D_{\rm P}$ $=$ 2 $\times$ 10$^{12}$ cm$^{-2}$ is used in Figs. 3 and 4.

Figure 2 illustrates the schematic cross section of the NB buffer SJ-LDMOS. The whole drift region is divided into five parts and their boundary positions are given by $x=0, x=L_{1}$, $x=L_{\rm D}$ and $y=0, y=t_{\rm SJ}$, $y=t_{\rm d}$, $y=h$. When the device is biased in the off-state configuration and the drift region is fully depleted, the potential function in the silicon film must be satisfied by the 2D Poisson equation, yielding:

$\begin{equation} \label{eq1} \frac{\partial ^2\phi _i ( {x, y})}{\partial x^2}+ \frac{\partial ^2\phi _i ( {x, y})}{\partial y^2}= -\frac{qN_i }{\varepsilon _{\rm si} }, \quad i=1, 2, 3, 4, 5, \end{equation}$

(1)

where $N_{1}=N_{2}=N_{\rm d}$ $+$ $N_{\rm N}-N_{\rm P}$ $=$ $N_{\rm d}$, $N_{3}=N_{4}=N_{\rm d}$, $N_{5}=N_{\rm b}$. The boundary conditions for $\phi_{i}(x, y)$ are given by:

$\begin{equation} \begin{cases} \label{eq2} \left. {\dfrac{\partial \phi _i ({x, y})}{\partial y}} \right|_{y=0} =0, \quad {i=1, 2}, \\[8mm] \left. \dfrac{\partial \phi _3({x, y})}{\partial y} \right|_{y=t_{\rm d}} = -\dfrac{2\phi _3 ({x, t_{\rm d}})}{t_{\rm sub}}, \\[8mm] \left. {\dfrac{\partial \phi _5 ({x, y})}{\partial y}} \right|_{y=h} =-\dfrac{2\phi _5({x, h})}{t_{\rm sub}}, \end{cases} \end{equation}$

(2)

$\begin{equation} \begin{cases} \label{eq3} \phi _{\rm 1}({x, t_{\rm sj}})=\phi _3({x, t_{\rm sj}}), \\[4mm] \left. {\dfrac{\partial \phi _1({x, y})}{\partial y}} \right|_{y=t_{\rm sj} } =\left. {\dfrac{\partial \phi _3({x, y})}{\partial y}} \right|_{y=t_{\rm sj}}, \end{cases} \end{equation}$

(3)

$\begin{equation} \begin{cases} \label{eq4} \phi _2({x, t_{\rm sj}})=\phi _4({x, t_{\rm sj}}), \\[4mm] \left. {\dfrac{\partial \phi _2({x, y})}{\partial y}} \right|_{y=t_{\rm sj} } =\left. {\dfrac{\partial \phi _4({x, y})}{\partial y}} \right|_{y=t_{\rm sj}}, \end{cases} \end{equation}$

(4)

$\begin{equation} \begin{cases} \label{eq5} \phi_4({x, t_{\rm d}})=\phi_5({x, t_{\rm d}}), \\[4mm] \left. {\dfrac{\partial \phi _4 ({x, y})}{\partial y}} \right|_{y=t_{\rm d}} =\left. {\dfrac{\partial \phi _5 ({x, y})}{\partial y}} \right|_{y=t_{\rm d}}, \end{cases} \end{equation}$

(5)

$\begin{equation} \begin{cases} \label{eq6} \phi _{\rm 1} ({0, 0})=0, \\[2mm] \phi _2 ({L_{\rm D}, 0})=V_{\rm d}, \\[2mm] \phi _1({L_1, 0})=\phi _2 ({L_1, 0}), \; \\[4mm] \left. {\dfrac{\partial \phi _{\rm 1} ({x, 0})}{\partial x}} \right|_{x=L_1 } =\left. {\dfrac{\partial \phi _2({x, 0})}{\partial x}} \right|_{x=L_1 } . \end{cases} \end{equation}$

(6)

The potential function $\phi_{i}(x, y)$ can be approximated by two-order Taylor expanded formula of

$\begin{equation} \label{eq7} \phi _i ({x, y})=\phi _i({x, 0})+ \frac{\partial \phi _i ({x, 0})}{\partial y}y+\frac{\partial ^2\phi _i ({x, 0})}{\partial y^2}\frac{y^2}{2}, \; i=1, 2, \end{equation}$

(7)

$\begin{equation} \begin{split} \label{eq8} \phi _i ({x, y})={}& \phi _i ({x, t_{\rm sj}})+\frac{\partial \phi _{i}({x, t_{\rm sj}})}{\partial y}\left( {y-t_{\rm sj} } \right) \\& +\frac{\partial ^2\phi _{i}({x, t_{\rm sj}})}{\partial y^2}\frac{({y-t_{\rm sj}})^2}{2}, \quad i=3, 4, \end{split} \end{equation}$

(8)

$\begin{equation} \begin{split} \label{eq9} \phi _5({x, y})={}& \phi _5({x, t_{\rm d}})+\frac{\partial \phi _5({x, t_{\rm d}})}{\partial y}\left( {y-t_{\rm d}} \right) \\& +\frac{\partial ^2\phi _5({x, t_{\rm d}})}{\partial y^2} \frac{({y-t_{\rm d}})^2}{2}. \end{split} \end{equation}$

(9)

Substituting Eqs. (7)-(9) into Eq. (1) under the boundary conditions (2)-(5) leads to a equation for the surface potential distribution function as follows,

$\begin{equation} \label{eq10} \frac{\partial ^2\phi _{i}({x, 0})}{\partial x^2}-\frac{\phi _{i}({x, 0})}{t_{i}^2}=-\frac{qN_{i, {\rm eff}}}{\varepsilon _{\rm si} }, \quad i=1, 2, \end{equation}$

(10)

where $N_{\rm 1, eff }=N_{\rm d}$, $N_{\rm 2, eff}= N_{\rm b}+(N_{\rm b}-N_{\rm d})$[$t_{\rm d}^{2}-(2h+t_{\rm s})t_{\rm d}$]/2$t_{2}^{2}$, $t_{1}$ $=$ [($t_{\rm d}^{2}+t_{\rm d}t_{\rm s})$/2]$^{1/2}$, $t_{2}$ $=$ [($h^{2}+ht_{\rm s})$/2]$^{1/2}$. Solving Eq. (10) with the boundary condition (6) yields the surface electric distribution as follows,

$\begin{equation} \label{eq11} \begin{split} E_i({x, 0}) = {}& \left( {V_{i} -\frac{qN_{i, {\rm eff}} t_{i}^2}{\varepsilon _{\rm si} }} \right) \frac{\cosh \left[{\left( {x-L_{i-1} } \right)/t_{i}} \right]} {t_{i} \sinh \left[{\left( {L_{i}-L_{i-1} } \right)/t_{i}} \right]} \\[2mm]& -\left( {V_{i-1} -\frac{qN_{i, {\rm eff}} t_i^2}{\varepsilon _{\rm si} }} \right) \frac{\cosh \left[{\left( {L_{i}-x} \right)/t_{i}} \right]}{t_{i} \sinh \left[{\left( {L_{i}-L_{i-1} } \right)/t_{i}} \right]}, \\[2mm]& \quad\quad\quad\quad \quad\quad\quad\quad \quad\quad\quad\quad L_{i-1} \leqslant x\leqslant L_{i}, \\ \end{split} \end{equation}$

(11)

where $L_{0}$ $=$ 0, $L_{2}=L_{\rm D}$. According to Eq. (11), it is easy to find that the surface electric field distribution can be modulated by parameters $N_{i, {\rm eff}}$ and $t_{i}$. It shows the theoretical explanation of the NB buffer SJ-LDMOS.

The key steps in the Bi-CMOS process are the formations of the N-buried layer and the surface shallow SJ pillars. The N-buried layer is realized by masked implantation of phosphorus in the P substrate before the epitaxial layer is formed on substrate. And the surface shallow SJ pillars are formed by ion implantation after field oxide formation. The main steps of one feasible fabrication method for the NB buffer SJ-LDMOS are given in Fig. 3 as follows: phosphorus ion implantation is implemented to form the N-buried layer. $L_{\rm b}$ is the length of the masking opening; epitaxial growth and phosphorus ions implantation are implemented to form an N-buffer layer; during high temperature processes in field oxide formation, the device is masked to prevent the formation of thick oxide above the N$^{-}$ drift region and a thick N-buffer layer is formed. Then a uniform, thin gate oxide is employed, which has a typical thickness of 200-1000 Å. One advantage of using such thin oxide is that it reduces the required energy for the ion implantation used to form the buried SJ layer; then phosphorus ions and boron ions are implanted to form the N pillar and the P pillar, respectively. The reason for forming the SJ region after field oxide formation is to avoid high temperature processes during the long time of the field oxide formation. It reduces thermal diffusion of impurities in the SJ region and suppresses dopant inter-diffusion between the P pillar and the N pillar effectively; and finally, deposit thick oxide and form the P$^{+}$ contact, the N$^{+}$ source/drain regions, and electrodes.

3. Result and discussion

The three-dimensional (3D) device simulations carried out by Sentaurus^[15] were performed in order to demonstrate the performances of the NB buffer SJ-LDMOS. In Fig. 4 the potential distribution for the NB buffer SJ-LDMOS, buffer SJ-LDMOS and the conventional SJ-LDMOS are compared. It is clear that the equipotential contours of the NB buffer SJ-LDMOS are evenly spaced and the depletion area extends deeper into the substrate, in comparison with those of buffer SJ-LDMOS and the conventional SJ-LDMOS. The BV of the NB buffer SJ-LDMOS reaches 350 V compared with 120 V of the conventional SJ-LDMOS, which is increased by about 190%.

Figure 5(a) shows the lateral electric field profiles at the silicon surface and at the top surface of the N-buried layer. A fair accordance between the analytical and numerical results may generally be found except the place near junctions due to the neglect of curvature of junctions in this model. The N-buffer layer suppresses the SAD effect. The surface lateral electric field distribution of the buffer SJ-LDMOS is therefore much more uniform than that of the conventional SJ-LDMOS. There is another electric field peak $P_{\rm K}$ at D$_{1}$ junction. Due to the electric field modulation effect of this new electric field peak, the surface lateral electric field strength of the NB buffer SJ-LDMOS in the middle of drift region is higher than that of the buffer SJ-LDMOS. Figure 5(b) shows vertical electric field distribution near the drain end. A new electric field peak ($E_{\rm C})$ is brought at the NB/substrate junction (i.e. D$_{2}$ junction). Thus the D$_{2}$ junction sustains a higher blocking voltage and BV can be improved.

The thickness of the N$^{-}$ buffer layer and the N-buried layer are limited by the thermal budget of the process. The doping doses of the N$^{-}$ buffer layer and the N-buried layer must ensure charge balance among the N pillar, the P pillar, the N-buffer layer, the N-buried layer, and the P substrate that is

$\begin{equation} \label{eq12} D_{\rm t} =D_{\rm d} +\frac{L_{\rm b}}{L_{\rm D}} D_{\rm b} \approx {\rm const}, \end{equation}$

(12)

where $D_{\rm t}$ is the total implantation dose, const is a constant which is equal to 1.6 $\times$ 10$^{12}$ cm$^{-2}$ in this brief (see Fig. 5(a)).

The influences of $D_{\rm t}$ and $L_{\rm b}$ on BV are shown in Fig. 6(a). It can be observed that the charge balance among the N pillar, the P pillar, the N-buffer layer, the N-buried layer, and the P substrate is achieved when $D_{\rm t}$ $=$ 1.6 $\times$ 10$^{12}$ cm$^{-2}$. And maximum BV is obtained at $L_{\rm b}=L_{\rm D}$/3. Hence, in the discussion below, the values of the $D_{\rm t}$ and the $L_{\rm b}$ are fixed at 1.6 $\times$ 10$^{12}$ cm$^{-2}$ and $\frac{1}{3}$ $L_{\rm D}$ respectively. The BV as a function of $D_{\rm b}$ is shown in Fig. 6(b). A well-designed $D_{\rm b}$ makes the modulation effect obvious but prevents the premature breakdown at D$_{1}$ or D$_{2}$ junction. According to Eq. (1), the $D_{\rm d}$ decreases with the increase of the $D_{\rm b}$ which leads to an increase in $R_{\rm on, sp}$. To obtain the trade-off between BV and $R_{\rm on, sp}$, the optimal range of the $D_{\rm b}$ is 2.1 $\times$ 10$^{12}$ $\leqslant$ $D_{\rm b}$ $\leqslant$ 2.7 $\times$ 10$^{12}$ cm$^{-2}$. In Fig. 6(c) the influences of the charge imbalance of the SJ region on the BV for the NB buffer SJ-LDMOS and the conventional SJ-LDMOS are compared. The NB buffer SJ-LDMOS shows a charge balance at maximum BV, while the conventional SJ-LDMOS shows a charge imbalance of 80%. The maximum BV of the NB buffer SJ-LDMOS increases $\Delta V$ ($\Delta V$ $=$ 120 V) compared with that of the conventional SJ-LDMOS.

The dependences of BV and $R_{\rm on, sp}$ on $L_{\rm D}$ for the NB buffer SJ-LDMOS, the buffer SJ-LDMOS, and the conventional SJ-LDMOS are shown in Fig. 7. The values of the power figure of merit (FOM; FOM $=$ BV$^{2}$/$R_{\rm on, sp})$ for the devices above are given in Table 1. It is found that the BV of the NB buffer SJ-LDMOS increases faster and saturates at a longer $L_{\rm D}$ with the increase of $L_{\rm D}$ (BV $>$ 700 V at $L_{\rm D}$ $=$ 55 $\mu$m). And the $R_{\rm on, sp}$ of the NB buffer SJ-LDMOS is much lower than that of the conventional SJ-LDMOS. Although the $R_{\rm on, sp}$ of the NB buffer SJ-LDMOS is higher than that of the buffer SJ-LDMOS due to the lower doping concentration of N-buffer layer in the NB buffer SJ-LDMOS, the FOM value of the NB buffer SJ-LDMOS is the highest which means the performance of the NB buffer SJ-LDMOS is superior to the other bulk Si devices.

4. Conclusion

A novel buffer SJ-LDMOS with an N-type buried layer is proposed and investigated by simulation. The N-buffer layer suppresses the SAD effect and the new electric field peaks caused by the N-buried layer modulates the surface electric field. The higher off-state BV is obtained. In addition, because of the shallow depth of the SJ pillars, the structure is compatible with Bi-CMOS technology. The NB buffer SJ-LDMOS exhibits an $R_{\rm on, sp}$ of 21 m$\Omega$$\cdot$cm$^{2}$ and a BV of 350 V, yielding an FOM of 5.8 mW/cm$^{2}$.