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Xiao Ma, Zhankun Du, Chang Liu, Ke Liu, Yuepeng Yan, Tianchun Ye. A fractional-N frequency synthesizer for wireless sensor network nodes[J]. Journal of Semiconductors, 2014, 35(12): 125003. doi: 10.1088/1674-4926/35/12/125003
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X Ma, Z K Du, C Liu, K Liu, Y P Yan, T C Ye. A fractional-N frequency synthesizer for wireless sensor network nodes[J]. J. Semicond., 2014, 35(12): 125003. doi: 10.1088/1674-4926/35/12/125003.
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A fractional-N frequency synthesizer for wireless sensor network nodes
DOI: 10.1088/1674-4926/35/12/125003
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Abstract
This paper presents a fractional-N frequency synthesizer for wireless sensor network (WSN) nodes. The proposed frequency synthesizer adopts a phase locked loop (PLL) based structure, which employs an LC voltage-controlled oscillator (VCO) with small VCO gain (KVCO) and frequency step (fstep) variations, a charge pump (CP) with current changing in proportion with the division ratio and a 20-bit Δ Σ modulator, etc. To realize constant KVCO and fstep, a novel capacitor sub-bands grouping method is proposed. The VCO sub-groups' sizes are arranged according to the maximal allowed KVCO variation of the system. Besides, a current mode logic divide-by-2 circuit with inside-loop buffers ensures the synthesizer generates I/Q quadrature signals robustly. This synthesizer is implemented in a 0.13 μm CMOS process. Measurement results show that the frequency synthesizer has a frequency span from 2.07 to 3.11 GHz and the typical phase noise is -86.34 dBc/Hz at 100 kHz offset and -114.17 dBc/Hz at 1 MHz offset with a loop bandwidth of about 200 kHz, which meet the WSN nodes' requirements.-
Keywords:
- WSN,
- frequency synthesizer,
- KVCO variation,
- divide-by-2
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References
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