1. Introduction

Much literature has been presented about current-steering digital-to-analog converters (DACs) for wide application including wireless communication. The system-on-chip (SOC) for wireless transceivers needs high performance baseband DAC occupying a small area, consuming very low power, and implemented in nanometer CMOS technology. To achieve good dynamic range with very small area, one technique named random rotation-based binary-weighted selection (RRBS) is proposed in Ref.[1] instead of intrinsic matching of current cell array. It occupies the smallest area of 10-bit current-steering DAC as far as the authors know. However, it compromises the static parameters INL and DNL.

In this work, the design methodology of intrinsic matching DAC is explored to design a very small DAC which meets the static and dynamic performance. In the following sections, a Monte Carlo model is built to analyze the impact of current source mismatch on INL yield. A formula is derived for the relation of INL and output impedance for a differential output current-steering DAC, and the relation of dynamic range and output impedance is analyzed.

Based on those analyses, the proposed 10 bit 250 MS/s current-steering DAC achieves intrinsic 10-bit accuracy and good dynamic performance in the 65 nm GP CMOS process, operating from a single 1.0 V supply, and occupying 0.06 mm$^{2}$ only. The single 1.0 V supply limits the available overdrive voltage of MOS transistors, thus it becomes difficult to design current-steering DAC in a small area because of the increased impact of $V_{\rm T}$ mismatch. Furthermore, it is hard to achieve high output impedance with nanometer GP CMOS process, especially when the cascode transistors and the switch transistors have minimum length. The gate leakage of core transistors cannot be ignored in the 65 nm GP CMOS process. It even becomes so severe that conventional bias circuitry (current mirror) malfunctions due to the huge total gate area of the current source array. An adapted current mirror is used to overcome the gate leakage in the current source array. The double centroid layout is adopted for the current source array.

2. Statistic yield model

The statistic yield model determines the area of unit current source, and eventually determines the area of current-steering DACs. In order to achieve 99.7% yield specification at INL < 1/2 LSB for a 10 bit DAC, the standard deviation of the unity current source must be less than 0.5% based on Bosch's analytical relation^[2]. It is derived with the equation

$\frac{\sigma (I)}{I}\leqslant \frac{1}{2C\sqrt {2^N}}\quad {\rm with}\quad C={\rm inv\_norm} \left(0.5+\frac{{\rm yield}}{2}\right),$

(1)

where $\sigma (I)/I$ is standard deviation of a unity current source, $N$ is the resolution of DAC, inv_norm is inverse cumulative normal distribution function, and yield is relative number of DAC with max INL < 1/2 LSB. However, that is somewhat pessimistic compared to the following Monte Carlo model, which gets more accurate $\sigma (I)/I$.

In a Monte Carlo model each unity current source has a Gaussian distributed random value. All the current sources are grouped into thermometer segment and binary segment. INL is calculated with both end-point line and best-fit line. The result of 10, 000 times Monte Carlo simulation is depicted in Fig. 1, where INL yield derived with Bosch's model^[2] is plotted for comparison. The Monte Carlo model has more relaxed requirement on $\sigma (I)/I$. Furthermore, the INL yield calculated with best-fit line is much better than that calculated with end-point line.

For 10 bit current-steering DACs, $\sigma (I)/I$ must be less than 1.25% for 99.7% yield of INL < 0.5 LSB according to the Monte Carlo model of best-fit line INL, and 0.85% according to the Monte Carlo model of end-point line INL as shown in Fig. 1. The gate area of one unity current source is determined by the well-established matching property model of MOS transistor^[3],

$(WL)_{\rm min} ={\frac{1}{2} \left[{A_\beta ^2 +\frac{4A_{\rm VT}^2 }{(V_{\rm GS}-V_{\rm T})^2}} \right]} \Bigg/{\left( {\frac{\sigma I}{I}} \right)}^2,$

(2)

where $A_{\rm VT}$ and $A_\beta$ are technology parameters for mismatch, and $V_{\rm GS} -V_{\rm T}$ is overdrive voltage. Therefore, for a specific process and overdrive voltage, the gate area of a unity current source predicted with the Monte Carlo model of best-fit line is 16% and 46% only of that predicted with Bosch's model and Monte Carlo model of end-point line, respectively. Thus it is feasible to implement the 10 bit DAC operating from a single 1.0 V supply in very small silicon area.

3. Output impedance

A simplified current-steering DAC with finite output impedance is shown in Fig. 2. The relationship between the output impedance and static performance is analyzed in Section 3.1; the relationship between the output impedance and dynamic performance is analyzed in Sections 3.2 and 3.3.

3.1 Output impedance and static performance

For the single-ended output the well-known relation for INL and output impedance is^[4]

${\rm INL} \approx \frac{R_{\rm L} N^2}{4R_0},$

(3)

where $R_{\rm L}$ is the load resistance, $N$ is the number of unity current source, and $R_{0}$ is the output resistance of one unity current source. However, Equation (3) is true for a single-ended output current-steering DAC only. The analytical INL model for a differential output current-steering DAC is developed here^[5]. The differential output voltage for code $k$ is

$V(k)=\frac{kI}{G_{\rm L} +kG_0 }-\frac{(N-k)I}{G_{\rm L} +(N-k)G_0},$

(4)

where $G_{\rm L}=1/R_{\rm L}$ and $G_{0}=1/R_{0}$. So INL for code $k$ is

${\rm INL}(k)=V(k)-V(0)-k\frac{V(N)-V(0)}{N}.$

(5)

Substituting Eq. (4) into Eq. (5) and assuming $G_{\rm L} \gg NG_0$ gives

${\rm INL}(k)\approx \frac{G_0^2 k(N-k)(N-2k)}{2G_{\rm L} (G_{\rm L} +NG_0)}.$

(6)

Thus INL has maximum value

$\left| {\rm INL} \right|_{\rm max} =\frac{G_0^2 }{2G_{\rm L} (G_{\rm L} +NG_0 )} \frac{\sqrt 3 N^2}{18},$

(7)

at $k=(6\pm \sqrt 3 )N/6$. For a 10 bit differential output DAC with 160 $\Omega$ load resistor at each output, the minimum output impedance for one unity current source is 3.6 M$\Omega$ with a view to INL less than 0.1 LSB, much smaller than the impedance 2.4 G$\Omega$ calculated using Eq. (3). The comparison of INL for differential output and single-ended output is plotted in Fig. 3, assuming the output impedance for one unity current source is 3.6 M$\Omega$, the load is 160 $\Omega$ at each output, and the DAC is 10 bit.

3.2 Output impedance and dynamic performance

The relation of output impedance and dynamic range is analyzed for differential output DAC, too^[5]. Compared to the static parameters analyzed in the aforementioned part, the dynamic performance is strongly related to the frequency-dependent output impedance of one unity current source. As shown in Fig. 2, the frequency-dependent conductance $g_{0}=(1/R_{0}+{\rm j}2\pi fC_{0})$/$A_{\rm sw}$, where $A_{\rm sw}$ is the small signal gain of the switch.

For a sinusoidal output signal, the conductance looking into the positive output is

$g_{\rm out+} =Ng_0 \frac{1+\sin (\omega t)}{2}.$

(8)

The conductance looking into the negative output is

$g_{\rm out-} =Ng_0 \frac{1-\sin (\omega t)}{2}.$

(9)

With the load conductance $g_{\rm L}=1/R_{\rm L}$, the output voltage at the positive output is

$V_{\rm out+} =N I\frac{1+\sin (\omega t)}{2g_{\rm L} +Ng_0 (1+\sin (\omega t))}.$

(10)

The output voltage at the negative output is

$V_{\rm out-} =N I\frac{1-\sin (\omega t)}{2g_{\rm L} +Ng_0 (1-\sin (\omega t))}.$

(11)

The Taylor series expansion of Eq. (10) is

$\begin{split} V_{\rm out+} = {}& a_0 +a_1 \sin (\omega t)+a_2 \sin ^2(\omega t)+a_3 \sin ^3(\omega t) \\& +a_4 \sin ^4(\omega t)+\cdots, \end{split}$

(12)

and the Taylor series expansion of Eq. (11) is

$\begin{split} V_{\rm out-} = {}& a_0 -a_1 \sin (\omega t)+a_2 \sin ^2(\omega t)-a_3 \sin ^3(\omega t) \\& +a_4 \sin ^4(\omega t)+\cdots, \end{split}$

(13)

where the coefficients are

$a_0 =\frac{N I}{2g_{\rm L}+Ng_0},$

(14)

$a_1 =\left( {\frac{N I}{2g_{\rm L} +Ng_0 }} \right)^2\frac{2g_{\rm L} }{N I},$

(15)

$a_2 =\left( {\frac{N I}{2g_{\rm L} +Ng_0 }} \right)^3\frac{-4g_0 g_{\rm L} }{N I^2},$

(16)

$a_3 =\left( {\frac{N I}{2g_{\rm L} +Ng_0 }} \right)^4\frac{8g_0^2 g_{\rm L} }{N I^3},$

(17)

$a_4 =\left( {\frac{N I}{2g_{\rm L} +Ng_0 }} \right)^4\frac{-16g_0^3 g_{\rm L} }{N I^4}.$

(18)

Thus the differential output signal is

$V_{\rm out+} -V_{\rm out-} =2[a_1 \sin (\omega t)+a_3 \sin ^3(\omega t)+\cdots].$

(19)

Obviously Equation (19) is an odd function. Thus the differential output has odd harmonics only. The fundamental is

${\rm Fund}=2\left( {a_1 +\frac{3}{4}a_3 } \right),$

(20)

and the third harmonic is

${\rm HD}_3 =\frac{1}{2}a_3.$

(21)

Since $g_{\rm L}$ is much greater than $g_{0}$, the ratio of the 3rd harmonic HD$_{3}$ and the fundamental signal is approximately^{[6, 7]}

$Q_3 \approx 2\left( {\frac{Ng_0 }{2g_{\rm L} }} \right)^2=2\left( {\frac{NZ_{\rm L} }{2Z_0 }} \right)^2,$

(22)

where $Z_{\rm L}$ and $Z_{0}$ are frequency-dependent output impedance of load and one unity current source, respectively.

3.3 Differential capacitive charge transfer and dynamic performance

Another mechanism called differential capacitive charge transfer was reported in Ref.[8]. A current cell illustrated in Fig. 2 is connected to either positive output or negative output. The total capacitance connected to the positive output is

$C_+ =\frac{NC_0 \left( {1+\sin \left( {\omega t} \right)} \right)}{2}.$

(23)

The total capacitance connected to the negative output is

$C_- =\frac{NC_0 \left( {1-\sin \left( {\omega t} \right)} \right)}{2}.$

(24)

During a cycle, the current cells are switched to positive output from negative output, the voltage on their capacitors C$_{0}$ varies and causes nonlinear voltage.

$V_{\rm nl} =\frac{1}{g_{\rm L}} \frac{\delta Q}{\delta t}=\frac{1}{g_{\rm L}} \frac{\left( {V_{\rm out+} -V_{\rm out-} } \right)}{A_{\rm sw} } \frac{\delta C}{\delta t}.$

(25)

Combine Eq. (23) to Eq. (25), when the positive output is rising

$V_{\rm nl} =2\pi f\frac{N^2C_0 I}{A_{\rm sw} g_{\rm L}^2 } \frac{\sin (4\pi ft)}{4},$

(26)

and when the negative output is rising

$V_{\rm nl} =-2\pi f\frac{N^2C_0 I}{A_{\rm sw} g_{\rm L}^2} \frac{\sin (4\pi ft)}{4}.$

(27)

The 3rd harmonic is

${\rm HD}_3 =-2\pi f\frac{N^2C_0 I}{A_{\rm sw} g_{\rm L}^2 } \frac{4}{5\pi}.$

(28)

Based on this mechanism, the ratio of the third harmonic and signal is

$Q_3 =2\pi f\frac{NC_0 }{A_{\rm sw} g_{\rm L}}\frac{4}{5\pi}.$

(29)

Equation (29) puts more stringent requirement on the output impedance for HD$_{3}$ than Eq. (22), and it dominates the dynamic performance over most frequency range that we are interested in. In Eq. (29), $g_{\rm L}$ is chosen by the system application. The capacitance $C_{0}$ is mainly determined by the gate source capacitance of the switch, which is approximately

$C_0 =\frac{2}{3}C_{\rm ox} W_{\rm sw} L_{\rm sw},$

(30)

where $C_{\rm ox}$ is the unity gate capacitance of the switch transistor, $W_{\rm sw}$ and $L_{\rm sw}$ are the width and length of the switch transistor, respectively.

The square law model is used to derive the gain of the switch $A_{\rm sw}$.

$A_{\rm sw} =\sqrt {\frac{2\mu C_{\rm ox} W_{\rm sw} L_{\rm sw} }{I_{\rm DS} }} V_{\rm E},$

(31)

where $I_{\rm DS}$ is the drain current of the switch transistor, and $V_{\rm E}$ is the early voltage of the switch transistor.

Substitute Eqs. (30) and (31) into Eq. (29),

$Q_3 =2\pi f\frac{4N}{5\pi g_{\rm L} }\frac{2V_{\rm E} }{3}\sqrt {\frac{C_{\rm ox} W_{\rm sw} L_{\rm sw} I_{\rm DS} }{2\mu }}.$

(32)

It indicates that the switch must be set to minimum channel length in order to improve the dynamic performance, and the width of the switch must be as small as possible, too. Since the square law is used to derive the gain of the switch $A_{\rm sw}$, it implies that the switch should be kept in saturation region when it is on. This is in accordance with the requirement of Eq. (29).

4. Circuit and layout implementation

The DAC is composed of current source array, cascode transistors, switches, thermometer decoder, synchronization latch, and bias circuitry.

4.1 Current source array

The current source array adopts a 6-4 segmented architecture. It has double centroid layout. Q3 rotated walk switching scheme^[11] is adopted for each quadrant of the current source array. It mitigates the graded and parabolic errors caused by electrical, process and temperature gradients. Two dummy rows and columns are put along each side to reduce the edge effects. The size of current source is minimized with the aforementioned analysis. It is beneficial to the dynamic range because the drain capacitance of unity current source may affect the output impedance severely at relative low frequency.

4.2 Cascode transistors

The cascode transistors are put outside of the current source array in order to make the current source array compact. The compact layout of the current source array improves the matching of current sources and reduces the graded and parabolic errors. The cascode transistor is put adjacent to the switch in order to minimize the capacitance $C_{0}$ in Fig. 2, which is critical to the dynamic performance as indicated by Eq. (29).

4.3 Synchronization latch

The complementary outputs of synchronization latch are adjusted for a low crossover point, thus the PMOS switches are not turned off simultaneously^[9]. The schematic of the synchronization latch^[10] is shown in Fig. 4. Due to the crossover point of node S and node SN being lowered to the threshold of conducting the switch transistor, one switch transistor is turned off immediately after the other switch is turned on when the voltage of nodes S and SN go through that crossover point. This scheme reduces glitch energy because the switches source node is charged when both switches are turned off simultaneously and they introduce glitch when the switches source node is discharged. Of course the clocked MOS transistors are dimensioned to reduce the clock coupling when the data input does not vary. The clock tree to all synchronization switches is balanced to reduce the clock skew.

4.4 Bias circuitry

The gate leakage cannot be ignored because of the very thin oxide of the 65 nm GP CMOS process^[12]. The simulation reveals tens of $\mu$A gate leakage and the conventional current mirror cannot sustain suitable bias voltage for current source array, because the gate leakage current is sourced through M3 and M4 if the gate of MCS is tied to the drain of M3 in Fig. 5. An adapted current mirror is used for overcoming the gate leakage current, which is shown in Fig. 5^[13]. M1 and M2 are two source followers. The gate leakage of MCS flows in M2. The gate of M2 is driven by M1. In this scheme, the minimum supply is 2$V_{\rm GSP}+V_{\rm DSN}$. The voltage of the gate of M1 is

$V_{\rm x} =V_{\rm sup} -V_{\rm GS, MCS} -V_{\rm GS, M2} +V_{\rm GS, M1} \approx V_{\rm sup } -V_{\rm GS, MCS}.$

(33)

Thus it prevents M3 and M4 from operating in triode region, which may occur in a current mirror with a PMOS source follower tied to the gate of MCS from the drain of M3 because the supply is 1.0 V only.

5. Measurement results

The microphotograph of the DAC core on the test chip is depicted in Fig. 6. The blocks in the DAC are not discernable because it is covered by the power and ground planes using higher metal layers. It occupies 0.06 mm$^{2}$ silicon areas and consumes 2.5 mW at 250 MS/s sample rate, operating from a single 1.0 V supply.

The max INL are all less than 0.4 LSB for all 7 chips measured in the lab, which agrees well with the statistic yield model proposed in Section 2 and the relation for INL and output impedance in Section 3. A typical INL/DNL plot is depicted in Fig. 7, where DNL is 0.19 LSB and INL is 0.25 LSB. One screenshot of the spectrum analyzer for 121 MHz signal at 250 MS/s sampling rate is shown in Fig. 8. The SFDR versus signal frequency is shown in Fig. 9. The measured SFDR at 100 MS/s and 250 MS/s is compared with the expected SFDR with Eq. (29). It is kept above 57 dB over the entire Nyquist band at 250 MS/s sample rate. The SFDR of the 10 MHz signal are kept beyond 70 dB up to 1.25 GS/s as shown in Fig. 10.

Table 1 summarizes the performance of this work and compares it with other 10 bit DACs and one 14 bit DAC recently published. Two figures of merit (FOM)^{[14, 8]}

${\rm FOM1}=\frac{2^{2N}\times f_{\rm s} @({\rm SFDR}=6(N-1))}{P\times {\rm area}},$

(34)

${\rm FOM2}=\frac{2^{\frac{{\rm SFDR}_{\rm DC} }{6.02}}\times 2^{\frac{{\rm SFDR}_{\rm Nyquist} }{6.02}}\times f_{\rm clk} }{P-0.5\times I_{\rm load}^2 \times R_{\rm load}},$

(35)

are shown in Eqs. (34) and (35), where $N$ is the resolution, $P$ is the power consumption, area is the DAC core area, $f_{\rm s}$ is the signal frequency where SFDR drops 6 dB compared with the expected result (6N dB), $f_{\rm clk}$ is the clock frequency, SFDR$_{\rm DC}$ is the SFDR at low signal frequency, and SFDR$_{\rm Nyquist}$ is the minimum SFDR over the entire Nyquist band.

6. Conclusion

A 10 bit current-steering DAC is implemented in the 65 nm GP CMOS process with standard core devices (standard $V_{\rm T}$ 1.0 V transistor) only. It consumes 2.5 mW from a single 1.0 V supply when operating at 250 MS/s sample rate. It occupies 0.06 mm$^{2}$ silicon area, much smaller than most published 10 bit DACs. This work is realized based on extensive statistical analysis of INL yield versus mismatch of unity current source, and analysis of the effect of output impedance on INL and SFDR. An adapted current mirror is adopted for overcoming the gate leakage of the current source array. At last, FOMs are better than other current-steering DACs recently published.

Acknowledgment: The authors would like to thank Wang Biao and Chen Jun for valuable test support.