1. Introduction

Power management is a vital block for system-on-chip (SoC) applications, especially in portable products such as cellular phones, video cameras, and laptops. Consequently, low dropout regulators (LDO), which have advantages of low power consumption, low noise, low production cost, high PSR, and easy integration, have obtained considerable attention in the mobile battery-operated design. LDO is usually used to provide a precise power supply voltage, eliminate the effects of input supply ripples and suddenly changed current of the load.

To enhance the closed-loop stability, traditional low dropout regulators are usually realized with an off-chip capacitor equivalent series resistance (ESR), which generates an ESR zero to realize pole-zero cancellation. However, the stability in this method, which relies on the value of the ESR, will become a drawback when the load condition is changed. In order to eliminate the ESR and implement a full on-chip LDO, and to maintain the closed-loop stability, several methods have been developed. Rincon-Mora et al. proposed the efficient current buffer method^[1], and pole-zero doublet method^[2]. Leung et al. proposed a regulator with damping factor control frequency compensation^[3]. The regulator costs a large chip area due to three compensating capacitors. Gao et al. in Ref.[4] created a zero by frequency dependent voltage controlled current sources(VCCS) instead of ESR, but still needed a low ESR capacitor as co-existence of VCCS generated zero. Other methods such as employing a differentiator formed by a current amplifier and a capacitor in Ref.[5], using three folded-cascode current operational amplifier in Ref.[6], and applying AC-boosting and active-feedback frequency compensation (ACB-AFFC) in Ref.[7], have been reported recently. Nevertheless, these methods have intrinsic drawbacks due to more than one capacitor or complicated circuits.

Moreover, another research focus, power supply rejection (PSR) should be high enough to eliminate the effect of power supply spurs. Weak transconductance of the pass transistor, low DC gain and finite bandwidth are the main reasons for poor PSR^[9]. Several approaches have been proposed with the purpose of improving PSR: feed-forward ripple cancellation technique in Ref.[8], using cascade structures for pass transistor in Ref.[9], and adaptive bias to extend the bandwidth in Ref.[10]. By using these techniques, PSR can reach -50 to -60 dB, which has a good performance on filtering the power supply ripples.

In this paper, brief analyses about the stability of classical LDOs are described first. Then, a high PSR capacitor-free low dropout regulator, based on Miller capacitor compensation and $g_{\rm m}$ boosting technique, is proposed. The experimental measurement results are given in the next section and the conclusion is summarized in the last section.

2. Analysis of classical LDOs

A traditional LDO is composed of an error amplifier, a pass element, a feedback network (FN), a reference voltage generator, and loading ESR, as shown in Fig. 1.

The topology creates obviously two poles at the pass MOSFET (MP) output node and the error amplifier output node. The MP output pole $P_1$ is given by:

$P_1=\frac{1}{R_{\rm O}C_{\rm OUT}}, \quad R_{\rm O}=R_{\rm DS}/\!/(R_{\rm F1}+R_{\rm F2})/\!/R_{\rm L},$

(1)

where $R_{\rm DS}$ is the resistance between MP's drain and source. $P_1$ is the dominated pole because both $C_{\rm OUT}$ and $R_{\rm L}$ have considerable values in most applications. The error amplifier output pole $P_2$ at the gate of MP is another pole that affects the stability of the LDO. Usually, the size of MP is very large to get high current through the load, so the parasitic capacitors in MP should be considered for their contributions to $P_2$. The value of $P_2$ has to be defined by:

$P_2=\frac{1}{R_{\rm o1}[C_{\rm o1}+C_{\rm GS}+(1+g_{\rm MP}R_{\rm O})C_{\rm GD}]},$

(2)

where $g_{\rm MP}$ denotes MP's transconductance.

From Eqs. (1) and (2), we can get two poles both located in the GBW at low frequencies, which influence the stability of the closed-loop.

Fortunately, a zero $Z_1$ is generated by the off-chip capacitor equivalent series resistance (ESR), which can compensate the influence of the second pole $P_2$ and enhance the stability of the classical LDO.

As illustrated in Fig. 2, the LDO will become unstable when the zero $Z_1$ move to the location at high frequency or beyond the unity gain frequency denoted as $Z_1'$.

To achieve reliable closed-loop stability, either $P_1$ or $P_2$ should be pushed to higher frequency in circuit design. However it is difficult to effectively move both $P_1$ and $P_2$ because of the large off-chip capacitor $C_{\rm OUT}$ and the large size of MP in common applications. Sacrificing the gain of error amplifier or power consumption to push poles to higher frequency are unsatisfactory approaches for analog circuit designers.

3. Proposed LDO structure

3.1 Stability analysis of proposed LDO

A second stage buffer with $g_{\rm m}$ boosting technique and a Miller capacitor are applied in proposed LDO as shown in Fig. 3. The Miller capacitor $C_{\rm c}$ is utilized to connect the MP output and the error amplifier output. It makes the pole at the output of the first stage error amplifier become the dominant pole and the pole at the output of the MP become the second pole. The Miller capacitor has a very important "pole splitting" property^[11]. We can view the second stage buffer and MP as one circuit block which has transconductance denoted with $g'_{\rm m2}$. Then, the small signal model can be illustrated in Fig. 4 as same as a classical two-stage operational amplifier. The transfer function is given in Eq. (3).

$\begin{split} \frac{V_{\rm o}(s)}{V_{\rm in}(s)}= {}& g_{\rm m1}g'_{\rm m2}R_1R_2\left(1-\frac{C_{\rm c}}{g'_{\rm m2}}s\right) \\[1mm]& \times \big\{1+s[R_1(C_1+C_{\rm c}) \\[1.7mm]& +R_2(C_2+C_{\rm c})+g'_{\rm m2}R_1R_2C_{\rm c}] \\[1mm]& +s^2R_1R_2[C_1C_2+C_{\rm c}C_1+C_cC_2]\big\}^{-1}. \end{split}$

(3)

Two poles can be obtained as follows:

$P_1=\frac{1}{g'_{\rm m2}R_1R_2C'_{\rm c}},$

(4)

$P_2=\frac{g'_{\rm m2}C_{\rm c}}{C_1C_2+C_2C_{\rm c}+C_1C_{\rm c}}.$

(5)

Because the output capacitor of the first stage error amplifier $C_{1}$ is reduced by adopting a buffer as second stage, $C_{2}$ is much larger than $C_{1}$. Usually $C_{\rm c}$ is also designed to be much larger than $C_{1}$, so the $P_{2}$ can be approximately derived as:

$P_2=\frac{g'_{\rm m2}}{C_2}.$

(6)

By adjusting the transconductance $g'_{\rm m2}$ or the Miller capacitor $C_{\rm c}$, the pole $P_1$ is pushed to lower frequency while the pole $P_{2}$ is pushed to higher frequency. Besides, the transconductance of the second stage is boosted to be a large value and it is a contribution to enhance the DC gain and to get high PSR.

From the transfer function (3), an unexpected Right-Hand-Zero (RHZ) is induced by the feed-forward path $C_{\rm c}$:

$Z_1=\frac{g'_{\rm m2}}{C_{\rm c}}.$

(7)

The RHZ is at very high frequency because $g_{\rm m}$ boosting technique is employed in the second stage buffer. So the influence of the zero can be easily eliminated owing to the large $g'_{\rm m2}$.

From Fig. 3, there is another pole $P_3$ at the gate of the MP. The expression of $P_3$ can be derived referring to Eq. (2):

$P_3=\frac{1}{R_{\rm o2}[C_{\rm o2}+C_{\rm GS}+(1+g_{\rm MP}R_{\rm DS})C_{\rm GD}]},$

(8)

where $R_{\rm o2}$ is the output resistance of the second stage buffer. Compared to classical designs, where the DC gain is the product of the error amplifier's output resistance and the MP's parameter capacitor, and it requires that the output resistance should be high, $R_{\rm o2}$ is permitted to be a small value while maintaining a considerable gain in this design, because $g_{\rm m2}$ is boosted to a large value and has a good tradeoff with power consumption.

3.2 Improvement of the proposed LDO's PSR

PSR is defined as the transmission gain from input signal to output signal ($A_{\rm vin})$ divided by the transmission gain from power supply signal to output signal ($A_{\rm vdd})$. Input signal reflecting the $A_{\rm vin}$ should be added into the positive input terminal of the error amplifier (as $V_{\rm REF}$ in Fig. 5), and the power supply signal reflecting the $A_{\rm vdd}$ should be added into the input terminal of the LDO (as $V_{\rm IN}$ in Fig. 5). High PSR means that the LDO system should have a considerable $A_{\rm vin}$.

The proposed LDO as depicted in Fig. 3 has a second buffer stage with $g_{\rm m}$ boosting added in the middle of the error amplifier and the MP, which are two major contributions to $A_{\rm vin}$ of the traditional LDO as depicted in Fig. 1. The second buffer stage offers an additional transmission gain which is proportional to the transconductance $g_{\rm m2}$ to the proposed LDO and it will increase the $A_{\rm vin}$. According to Section 3.3, the transconductance of the second stage buffer is boosted by $k$ times to that transconductance in the same circuit without $g_{\rm m}$ boosting technique and consequently the PSR of the proposed LDO is improved efficiently.

3.3 Transistor-level implementation

The transistor-level of the proposed LDO is illustrated in Fig. 5. The left part is bias circuits with power down control transistors. The error amplifier is formed by five transistors M10-M14, whose one input comes from bandgap reference voltage ($V_{\rm REF}$), and the other input comes from feedback voltage. It makes a relation between the output voltage $V_{\rm OUT}$ and the $V_{\rm REF}$.

$V_{\rm REF}=V_{\rm OUT}\frac{R_{\rm F2}}{R_{\rm F1}+R_{\rm F2}}.$

(9)

The second stage is using a buffer with $g_{\rm m}$ boosting composed of seven transistors M20-M26. The technique of $g_{\rm m}$ boosting is realized by M25 and M26. If the voltage of the error amplifier output $V_{\rm O1}$ fluctuates by $\Delta V$, which transfers to the gate of M25, a voltage with the value of $-\Delta V$ will be added to signal $V_{\rm N}$ at the gate of M26 for the same transconductances of M25 and M26. The size of M22 is designed by $k$ times to the size of the M21, similarly the M24 compared to the M23. As we know, the transconductance $g_{\rm m}$ is proportional to the transistors' size $W/L$, so we can get:

$g_{\rm m22} \approx k g_{\rm m21},$

(10)

$g_{\rm m24} \approx k g_{\rm m23}.$

(11)

Additionally, for transistor M23 in Fig. 5, variations at the drain and gate are related as follows:

$V_{\rm d23}/V_{\rm g23}=-g_{\rm m23}/g_{\rm m21}.$

(12)

The drain to source current in transistor M22 can be derived using Eqs. (10) and (12):

$I_{\rm ds22} = k g_{\rm m23} V_{\rm g23},$

(13)

$I_{\rm ds24} =-(g_{\rm m25}/g_{\rm m26})g_{\rm m24}V_{\rm g25},$

(14)

$V_{\rm g23} =V_{\rm g25}=\Delta V.$

(15)

For the same transconductances of M25 and M26 and the same voltages at gates of M23 and M25, with Eqs. (11), (13), (14) and (15), the output voltage at the gate of MP ($V_{\rm O2})$ can be derived as:

$V_{\rm O2} =-2 k g_{\rm m23}\Delta V (r_{\rm ds22}//r_{\rm ds24}).$

(16)

The transconductance of the second stage buffer is boosted by $k$ times to that transconductance in the same circuit without $g_{\rm m}$ boosting technique, the closed-loop stability of the circuit is consequently enhanced, and the gate of MP can be driven to cut-off the transistor much more efficiently.

The PASS MOS transistor is designed large as mentioned before and resistances in the feedback network are formed by small resistance with the same value in series to guarantee concordant variations caused by manufacture and application of environmental conditions.

4. Simulation and measurement results

4.1 Simulation results

The proposed LDO was implemented in 0.18 $\mu$m CMOS technology, and post-layout simulations were covered by all corners and environmental conditions. When the AC signal is added into the error EA's positive input terminal labelled $V_{\rm REF}$ in Fig. 5, the frequency responses are simulated as shown in Fig. 6 to reflect the stability and location of poles and zeros of the LDO. The open-loop gain is higher than 110 dB when the load current varies from 0 to 50 mA, and it is also a high value of 106 dB when the load current is up to 100 mA. The phase margin is maintained at about 79 degrees, which can promise good closed-loop stability. The PSR results are shown in Fig. 7 which is obtained by adding AC signal to the LDO's input terminal labelled $V_{\rm IN}$ in Fig. 5. When the load current changes from 0 to 50 mA, the PSR values remain as at least -79 dB and change to -75 dB when load current is 100 mA. The PSR value can also be lower than -40 dB when frequency is 1 MHz and load current is 0 to 100 mA.

4.2 Fabrication and measurement results

The proposed LDO has been fabricated in standard 0.18 $\mu$m CMOS technology provided by GSMC (Shanghai, China). The active area is about 180 $\times$ 100 $\mu$m$^{2}$ excluding the pads and ESD circuits, whose chip photograph is shown in Fig. 8 taken by Olympus BX51WI-DPMC when the enlargement factor is set to be 200. The line regulation is measured by Tektronix oscilloscope DPO4104B. When the supply voltage transforms from 2.42 to 4.42 V as shown in channel 1, the upper half of Fig. 8, the output voltage changes about 5 mV as shown in channel 2, the lower half of Fig. 9. So the calculated line regulation is 2.5 mV/V. The measured output voltage of the LDO goes up to 1.79 V shown in Fig. 10 when the power supply varies from 1.5 to 2.5 V, then the output voltage is maintained at 1.79 V till the power supply voltage varies up to 5 V. The performance of the proposed regulator is summarized in Table 1.

5. Conclusion

A high PSR full on-chip CMOS low dropout regulator is proposed in this paper. The proposed LDO is fabricated in standard CMOS 0.18 $\mu$m technology. The pole splitting and $g_{\rm m}$ boosting technique are used to get good performance of stability and PSR. The proposed LDO can drive 100 mA load and chip area is only less than 0.02 mm$^{2}$. With these advantages, the proposed LDO is suitable for low power system-on-chip application.