1. Introduction
As is well known, high power microwave (HPM) can couple into integrated circuits (ICs) and systems either intentionally or unintentionally, and cause reversible upset or permanent damage such as burn-out[1]. With the development of IC technology and the increasingly complex electromagnetic environments, the electromagnetic interference (EMI) on electronic systems has been gaining interest recently[1-10]. It is confirmed that the latch-up effect is one of the common phenomenon in CMOS digital ICs working in complex environments like electromagnetic pulse (EMP), electrostatic discharge (ESD) and ion irradiation etc.
Some significant research results have been reported for latch up effects caused by HPM. In Ref.[5], the energy threshold characteristics of latch-up effects induced by HPM were given. Further, the interference effect of HPM was observed to be suppressed at higher frequency in Ref.[6]. The dependencies of latch-up susceptibility on pulse parameters were observed and verified by Refs.[7, 8]. All the experiments or simulations are usually implemented at a specific ambient temperature and under special operating conditions, and the influences of the device operating environment and status are hardly taken into account. Furthermore, the CMOS inverter may self-reset from latch-up and return to normal function after a delay time, which was reported in Ref.[9]. However, the microscopic interpretation was not given unfortunately, which is critical to theoretical study.
In this paper, the thermal effect is analyzed, aiming to facilitate the understanding of the latch-up mechanism. Further, the temperature dependence of latch-up effects caused by HPM is discussed at various ambient temperatures and under different heat dissipation conditions. Also, the delay time characteristics are revealed and explored. Finally, the effects of the pulse width at different ambient temperatures are discussed in detail. Compared with experimental methods, the simulation method in this paper can give a microscopic interpretation for the temperature dependence and the delay time characteristics in detail.
2. Test structure and model
2.1 Test structure
The basic schematic of a CMOS inverter consisting of a parasitic p-n-p-n structure is given in Fig. 1. The lateral device size (axis
2.2 Physical model
As depicted in Fig. 1, the P-substrate/n
The latch-up involves an intense electric field and a high current density, resulting in obvious temperature characteristics. Consequently, the model takes the electro-thermal coupling model and other physical models into account simultaneously based on ISE-TCAD[12]. In order to discuss the temperature dependence of the latch-up effects, the doping-dependent mobility model proposed by Arora et al.[13] for an extended temperature range (200-500 K) is adopted and revised as follows:
μdop=μmin+μd1+(NiN0)A∗, |
(1) |
with
μmin=Amin(TT0)αm, |
(2) |
where
3. Numerical simulation
For the test structure (Fig. 1), the normal input signal is a periodic square wave with a cycle of 20 ns, duty of 50% and the HPM pulse is a sinusoidal signal with a frequency of 1 GHz, a pulse width of 10 ns and a pulse repetition frequency (PRF) of 0. When HPM pulses with different power levels are exerted, the responses of the CMOS inverter are given in Fig. 2. When a HPM pulse with an average power of 10.8 dBm is on, the CMOS inverter responds in bit errors, but returns to normal function as soon as the HPM is removed. However, the output voltage sustains at about 1.2 V, even after the HPM pulse is removed as the power is up to 16.2 dBm, indicating that a malfunction has appeared.
To observe the latch-up effect visibly, the power supply current
4. Results and discussion
4.1 Thermal effect in CMOS inverter caused by HPM
In general, the interior temperature in the CMOS inverter maintains nearly at 300 K (room temperature) during normal operation and the thermal effect can be ignored. When a HPM with a power of 10.8 dBm is exerted, the maximum temperature increases obviously during the HPM action and comes back to room temperature gradually after the HPM is removed (as shown in Fig. 4). As the power is increased to 16.2 dBm, the temperature firstly increases and then decreases in a similar way to that with a power of 10.8 dBm before 12 ns. However, the temperature starts to increase again rapidly at 12 ns and soon rises to a high level, even causing burnout. The thermal process may be roughly divided into three segments (respectively for regions Ⅰ, Ⅱ and Ⅲ in Fig. 4).
As to the first segment, the temperature increases during the negative half period of the pulse but decreases slightly when the positive half period comes. The period from 7.5 to 8.5 ns (highlighted in Fig. 4) is taken as an example. When the negative half period arrives (at 7.5 ns), the P-substrate/n
After the HPM is removed, the maximum temperature decreases firstly and then increases again continuously, corresponding to the position of the hot spot from the cylinder of the p
4.2 Influence of the ambient temperature on latch-up
4.2.1 HPM susceptibility trend as a function of ambient temperature
In actual applications, the operating temperature of digital circuits usually varies between 100 K and 500 K due to the hazardous weather or special environments such as outer space and the moon. In order to explore the temperature dependence of latch-up, a HPM pulse with a frequency of 1 GHz, a width of 10 ns and a PRF of 0 is exerted on the CMOS inverter at various ambient temperatures. Based on the model constructed above, the variations of the power threshold and voltage amplitude causing latch-up are obtained. As Figure 7 reveals, the latch-up triggering power decreases by 7.4 dBm with the ambient temperature increasing from 150 to 400 K. The relationship between the triggering power threshold
P=ATβ, |
(3) |
where
The influence of ambient temperature obtained here can be verified with Ref.[15], which concludes the latch-up triggering voltage decreases with temperature increasing from 300 to 400 K. The comparison of the two results is shown in Fig. 7 by a normalization method, with the triggering voltage at 300 K is used as a reference. The data from this paper and the experimental results are in good agreement. In addition, the conclusion in this paper complements the susceptibility trend for an extended temperature range from 150 to 300 K, which is not available in the literature.
4.2.2 Variation of substrate resistance versus temperature
According to the physical model, three conditions must be fulfilled to sustain latch-up[16]: (1) the current flowing through the substrate and the substrate resistance must be large enough to forward bias the emitter-base junctions; (2) the common base current gain product of the parasitic transistors Q1 and Q2 must be sufficient to guarantee regeneration; (3) the power supply current must be greater than the holding current of the latch-up path. It is obvious that condition (3) can be satisfied in this investigation. The common base current gain of a bipolar junction transistor slightly increases with the temperature increasing and the opposite tendency holds for the forward-bias voltage. However, the change trends are not significant enough to cause the variation of
Generally, all the impurities in doping silicon can be ionized at a temperature between 100 and 500 K. The carrier density depends on the impurity concentration and sustains at a relatively constant value at various temperatures in this range[18]. By the expression of electrical conductivity
4.3 Influence of the temperature distribution on latch-up
4.3.1 The latch-up delay time characteristics
If latch-up occurs, it is mostly common that the suddenly reduced impedance and sharply increased power supply current results in the CMOS inverter continuously heating, suffering malfunction and even burning out. The other situation reported in Ref.[9] is that the device may recover from malfunction by self-reset after a delay time. Unfortunately, no detailed microscopic explanation is given in the literature. In order to interpret the latch-up delay time characteristics, the heat dissipation condition that the bottom side of the device, seen as an ideal heat sink, is defined as condition (1). In contrast, a thermal resistive boundary condition with 0.1 cm
4.3.2 Influence of the heat dissipation condition
As is well known, the heat dissipation condition has a significant effect on the temperature distribution. As Fig. 10 shows, the high temperature region covers a greater proportion of the P-substrate under condition (2) than condition (1). So the average temperature in the P-substrate will be higher under condition (2) and the carrier mobility in the P-substrate will be reduced substantially because of the elevated temperature (revealed in Fig. 11). The variation directly results in the electrical conductivity of the latch-up path decreasing and the impendence increasing by so high a level that the latch-up will be weakened and even finished.
The impact of temperature on latch-up will be more obvious in actual applications because the chips are generally packaged and fixed in the entire electronics system. Sometimes burnout even occurs under worse conditions.
4.4 Effects of pulse width at different ambient temperatures
The latch-up triggering power thresholds with incremental HPM pulse width
P=Bτα, |
(4) |
where
P=28.0τ−0.23,T=300K, |
(5) |
P=24.3τ−0.23,T=400K. |
(6) |
It is obvious that the
5. Conclusion
In this paper, the model including latch-up in the CMOS inverter based on 0.5