1. Introduction

As is well known, high power microwave (HPM) can couple into integrated circuits (ICs) and systems either intentionally or unintentionally, and cause reversible upset or permanent damage such as burn-out^[1]. With the development of IC technology and the increasingly complex electromagnetic environments, the electromagnetic interference (EMI) on electronic systems has been gaining interest recently^[1-10]. It is confirmed that the latch-up effect is one of the common phenomenon in CMOS digital ICs working in complex environments like electromagnetic pulse (EMP), electrostatic discharge (ESD) and ion irradiation etc.

Some significant research results have been reported for latch up effects caused by HPM. In Ref.[5], the energy threshold characteristics of latch-up effects induced by HPM were given. Further, the interference effect of HPM was observed to be suppressed at higher frequency in Ref.[6]. The dependencies of latch-up susceptibility on pulse parameters were observed and verified by Refs.[7, 8]. All the experiments or simulations are usually implemented at a specific ambient temperature and under special operating conditions, and the influences of the device operating environment and status are hardly taken into account. Furthermore, the CMOS inverter may self-reset from latch-up and return to normal function after a delay time, which was reported in Ref.[9]. However, the microscopic interpretation was not given unfortunately, which is critical to theoretical study.

In this paper, the thermal effect is analyzed, aiming to facilitate the understanding of the latch-up mechanism. Further, the temperature dependence of latch-up effects caused by HPM is discussed at various ambient temperatures and under different heat dissipation conditions. Also, the delay time characteristics are revealed and explored. Finally, the effects of the pulse width at different ambient temperatures are discussed in detail. Compared with experimental methods, the simulation method in this paper can give a microscopic interpretation for the temperature dependence and the delay time characteristics in detail.

2. Test structure and model

2.1 Test structure

The basic schematic of a CMOS inverter consisting of a parasitic p-n-p-n structure is given in Fig. 1. The lateral device size (axis $x$) and the depth (axis $y$) is 15 $\mu$m and 6 $\mu$m respectively and the CMOS inverter is constructed based on 0.5 $\mu$m CMOS technology. The power supply voltage is chosen as 5 V. Q1 and Q2 are respectively the parasitic NPN and PNP transistors, $R_{\rm sub}$ and $R_{\rm well}$ are the P-Substrate and N-well resistors respectively. Generally, the HPM radiation energy couples into the interior electronics of a system through either the front-door or back-door^[5] path. In this investigation, the HPM is assumed as a sinusoidal plane wave without attenuation^[10], and is injected into the "S" contact of the n-MOSFET to simulate the process that the HPM radiation energy couples into the basic unit (CMOS inverter) of the digital integrated circuits through the back-door path. The procedure with HPM injected into other contacts is similar. In addition, adiabatic thermal boundary conditions are used at the top and lateral sides and a constant ambient temperature (300 K) is set at the bottom side.

2.2 Physical model

As depicted in Fig. 1, the P-substrate/n$^+$ source junction is triggered into forward bias during the negative half period of the exerted HPM pulse. An amount of carriers is injected into the P-substrate and most of the minority carriers will recombine with the majority carriers in the P-substrate and the rest will be collected by the N-well, producing the corresponding current $I_{\rm sub}$ and $I_{\rm well}$^[11]. The current will flow through $R_{\rm sub}$ ($R_{\rm well})$ and then produce a voltage drop. If this voltage drop is large enough, it can forward bias the emitter-base junction of Q1 (Q2) and then the transistor turns on. Once one turns on, the other can also turn on via the mechanism of positive regeneration feedback. If the product of the two transistors' common base current gain is larger than the unit, the positive feedback mechanism can be maintained, leading to a large current conducting through a low-impedance path from the power supply trail to the ground (GND).

The latch-up involves an intense electric field and a high current density, resulting in obvious temperature characteristics. Consequently, the model takes the electro-thermal coupling model and other physical models into account simultaneously based on ISE-TCAD^[12]. In order to discuss the temperature dependence of the latch-up effects, the doping-dependent mobility model proposed by Arora et al.^[13] for an extended temperature range (200-500 K) is adopted and revised as follows:

$\begin{equation} \label{eq1} \mu _{\rm dop} =\mu _{\rm min} +\frac{\mu _{\rm d} }{1+\left( {\dfrac{N_i }{N_0 }} \right)^{A^\ast }}, \end{equation}$

(1)

with

$\begin{equation} \mu _{\rm min} =A_{\rm min } \left( {\frac{T}{T_0 }} \right)^{\alpha _m }, \end{equation}$

(2)

where $N_{\rm i}$ denotes the total concentration of ionized impurities, $T_{0}$ $=$ 300 K, and $T$ is the lattice temperature. Similarly, $\mu _{\rm d}$, $N_0$ and $A^\ast$ have the same forms as $\mu _{\rm min}$ but different coefficients. All the four variables in Eq. (1) depend on the temperature and hence make the physical model more able to accurately predict the temperature dependence of latch-up effects.

3. Numerical simulation

For the test structure (Fig. 1), the normal input signal is a periodic square wave with a cycle of 20 ns, duty of 50% and the HPM pulse is a sinusoidal signal with a frequency of 1 GHz, a pulse width of 10 ns and a pulse repetition frequency (PRF) of 0. When HPM pulses with different power levels are exerted, the responses of the CMOS inverter are given in Fig. 2. When a HPM pulse with an average power of 10.8 dBm is on, the CMOS inverter responds in bit errors, but returns to normal function as soon as the HPM is removed. However, the output voltage sustains at about 1.2 V, even after the HPM pulse is removed as the power is up to 16.2 dBm, indicating that a malfunction has appeared.

To observe the latch-up effect visibly, the power supply current $I_{\rm dd}$ in three cases are depicted in Fig. 3. $I_{\rm dd}$ basically sustain at zero during normal operation, except there is a slight wave motion while the CMOS inverter flips. When a HPM with a power of 10.8 dBm is exerted, the current increases slightly but is still less than 1 mA. As the power increases to 16.2 dBm, the situation becomes absolutely different and $I_{\rm dd}$ increases to nearly 45 mA at 10 ns, more than 50 times of that with a power of 10.8 dBm. The malfunction and sharply increasing power supply current may serve as the latch-up criterion, based on which the latch-up characteristics, such as the triggering power threshold characteristic, can be obtained.

4. Results and discussion

4.1 Thermal effect in CMOS inverter caused by HPM

In general, the interior temperature in the CMOS inverter maintains nearly at 300 K (room temperature) during normal operation and the thermal effect can be ignored. When a HPM with a power of 10.8 dBm is exerted, the maximum temperature increases obviously during the HPM action and comes back to room temperature gradually after the HPM is removed (as shown in Fig. 4). As the power is increased to 16.2 dBm, the temperature firstly increases and then decreases in a similar way to that with a power of 10.8 dBm before 12 ns. However, the temperature starts to increase again rapidly at 12 ns and soon rises to a high level, even causing burnout. The thermal process may be roughly divided into three segments (respectively for regions Ⅰ, Ⅱ and Ⅲ in Fig. 4).

As to the first segment, the temperature increases during the negative half period of the pulse but decreases slightly when the positive half period comes. The period from 7.5 to 8.5 ns (highlighted in Fig. 4) is taken as an example. When the negative half period arrives (at 7.5 ns), the P-substrate/n$^+$ source junction becomes forward bias. Then the current path from the P-substrate contact to the n$^+$ source contact forms and flows through the cylinder of the p$^+$ region, where the highest current density is located (depicted as Fig. 5(a)). Meanwhile, the most intense electric field intensity exists on the same cylinder due to the minimum radius of curvature here^[14]. The heat $Q$ generated in the transistors is determined by both the current density $J$ and the electric field intensity $E$. Hence the heat generated is bound to exceed that diffusing outwards. When the positive half period arrives (8 ns), the P-substrate/n$^+$ source junction becomes reverse biased, yet the current path from the P-substrate contact to the n$^+$ source does not form (Fig. 5(b)) and hence the temperature decreases.

After the HPM is removed, the maximum temperature decreases firstly and then increases again continuously, corresponding to the position of the hot spot from the cylinder of the p$^+$ region (Fig. 6(a)) to another (Fig. 6(b)). At 10 ns, latch-up has occurred and the new current path from the power supply trail to the GND forms, as depicted in Fig. 6(c). The voltage dropping on the reverse biased p$^+$ drain/N-well junction is large, resulting in a strong electric field intensity here. It can be seen that the 1st hot spot may cause burnout directly if the HPM power is high enough. If not, damage may also occur indirectly due to the 2nd hot spot.

4.2 Influence of the ambient temperature on latch-up

4.2.1   HPM susceptibility trend as a function of ambient temperature

In actual applications, the operating temperature of digital circuits usually varies between 100 K and 500 K due to the hazardous weather or special environments such as outer space and the moon. In order to explore the temperature dependence of latch-up, a HPM pulse with a frequency of 1 GHz, a width of 10 ns and a PRF of 0 is exerted on the CMOS inverter at various ambient temperatures. Based on the model constructed above, the variations of the power threshold and voltage amplitude causing latch-up are obtained. As Figure 7 reveals, the latch-up triggering power decreases by 7.4 dBm with the ambient temperature increasing from 150 to 400 K. The relationship between the triggering power threshold $P$ and the ambient temperature $T$ can be described by the power-law equation as follows:

$\begin{equation} \label{eq2} P=A T^\beta, \end{equation}$

(3)

where $A$ and $\beta$ denote the coefficients to be determined by the experiments, $P$ is in dBm, and $T$ is in K. The coefficients $A$ $=$ 190, and $\beta$ $=$ $-0.43$ are for the device operating under conditions in this investigation. The $R$-square ($R^{2})$ is 0.99, showing a high degree of correlation between the triggering power and the ambient temperature. It can be concluded that CMOS inverters operating at the higher ambient temperature are more susceptible to HPM and the dependence is slightly reduced at higher temperatures.

The influence of ambient temperature obtained here can be verified with Ref.[15], which concludes the latch-up triggering voltage decreases with temperature increasing from 300 to 400 K. The comparison of the two results is shown in Fig. 7 by a normalization method, with the triggering voltage at 300 K is used as a reference. The data from this paper and the experimental results are in good agreement. In addition, the conclusion in this paper complements the susceptibility trend for an extended temperature range from 150 to 300 K, which is not available in the literature.

4.2.2   Variation of substrate resistance versus temperature

According to the physical model, three conditions must be fulfilled to sustain latch-up^[16]: (1) the current flowing through the substrate and the substrate resistance must be large enough to forward bias the emitter-base junctions; (2) the common base current gain product of the parasitic transistors Q1 and Q2 must be sufficient to guarantee regeneration; (3) the power supply current must be greater than the holding current of the latch-up path. It is obvious that condition (3) can be satisfied in this investigation. The common base current gain of a bipolar junction transistor slightly increases with the temperature increasing and the opposite tendency holds for the forward-bias voltage. However, the change trends are not significant enough to cause the variation of $V_{\rm trig}$ as depicted above^[17].

Generally, all the impurities in doping silicon can be ionized at a temperature between 100 and 500 K. The carrier density depends on the impurity concentration and sustains at a relatively constant value at various temperatures in this range^[18]. By the expression of electrical conductivity $\sigma =nq\mu$, the variation of the P-Substrate resistance mainly depends on the carrier mobility $\mu$ as long as the temperature does not exceed 500 K. Following the mobility model in Section 2.2, the carrier mobility decreases with the temperature increasing and the variation of the substrate resistance is the reverse. In Fig. 8, the electron mobility and the P-substrate resistance values during the latch-up at incremental ambient temperature are extracted and revealed. According to condition (1), the significantly increasing substrate resistance brings about an easily triggered latch-up.

4.3 Influence of the temperature distribution on latch-up

4.3.1   The latch-up delay time characteristics

If latch-up occurs, it is mostly common that the suddenly reduced impedance and sharply increased power supply current results in the CMOS inverter continuously heating, suffering malfunction and even burning out. The other situation reported in Ref.[9] is that the device may recover from malfunction by self-reset after a delay time. Unfortunately, no detailed microscopic explanation is given in the literature. In order to interpret the latch-up delay time characteristics, the heat dissipation condition that the bottom side of the device, seen as an ideal heat sink, is defined as condition (1). In contrast, a thermal resistive boundary condition with 0.1 cm$^{2}$K/W surface thermal resistance set at the bottom side is defined as condition (2). Similarly, the same HPM pulse with a frequency of 1 GHz, a width of 10 ns and a PRF of 0 is injected into CMOS inverters (at 300 K). As depicted in Fig. 9 under heat dissipation condition (1), bit errors appear and $I_{\rm dd}$ increases acutely during the HPM action. Besides, after the HPM is removed, the CMOS inverter cannot normally respond to the input yet. However, the situation under condition (2) differs. Though latch-up occurs, the output voltage increases to 5 V gradually and $I_{\rm dd}$ returns to zero after a delay time of about 720 ns, meaning latch-up ends and the delay time characteristic appears. The result demonstrates the delay time characteristics reported in Ref.[9] are closely related to the heat dissipation condition.

4.3.2   Influence of the heat dissipation condition

As is well known, the heat dissipation condition has a significant effect on the temperature distribution. As Fig. 10 shows, the high temperature region covers a greater proportion of the P-substrate under condition (2) than condition (1). So the average temperature in the P-substrate will be higher under condition (2) and the carrier mobility in the P-substrate will be reduced substantially because of the elevated temperature (revealed in Fig. 11). The variation directly results in the electrical conductivity of the latch-up path decreasing and the impendence increasing by so high a level that the latch-up will be weakened and even finished.

The impact of temperature on latch-up will be more obvious in actual applications because the chips are generally packaged and fixed in the entire electronics system. Sometimes burnout even occurs under worse conditions.

4.4 Effects of pulse width at different ambient temperatures

The latch-up triggering power thresholds with incremental HPM pulse width $\tau$ are acquired at different ambient temperatures, as depicted in Fig. 12. It indicates that the triggering power threshold increases with the decrease in pulse width. It is found that the relationship of $P$ with $\tau$ meets the following power-law function:

$\begin{equation} \label{eq3} P=B\tau ^\alpha, \end{equation}$

(4)

where $B$ and $\alpha$ represent the coefficients to be determined by experiments. As shown in Fig. 12, the power threshold with a certain pulse width at 300 K is higher than that at 400 K. Using the curve fitting method, the two sets of data points respectively at 300 K and 400 K can be described as follows:

$\begin{equation} P=28.0\tau ^{-0.23}, \quad T=300\, {\rm K}, \end{equation}$

(5)

$\begin{equation} P=24.3\tau ^{-0.23}, \quad T=400\, {\rm K}. \end{equation}$

(6)

It is obvious that the $\alpha$ values at two ambient temperatures are the same while the $B$ values are different, meaning that the degree of change with the incremental pulse width at different ambient temperatures is constant, though CMOS inverters at higher temperatures are more susceptible to HPM. Meanwhile, it can be concluded from Fig. 12 that more energy will be absorbed to cause latch-up at a lower ambient temperature, but at a certain temperature, the energy is basically sustained at a constant value (about 0.5 nJ at 300 K).

5. Conclusion

In this paper, the model including latch-up in the CMOS inverter based on 0.5 $\mu$m technology is constructed. The malfunction, current characteristics and the delay time characteristic are revealed by simulation. The thermal effect is analyzed in detail. Further, the temperature dependence of latch-up effects induced by HPM is discussed at various ambient temperatures and under different heat dissipation conditions. It is concluded that CMOS inverters operating at higher ambient temperatures are more susceptible to HPM. The conclusion is verified by the experimental data from previous literature and expands on the literature's original conclusion. By the curve fitting method, a power-law equation $P=AT^{\beta}$ is obtained to describe the dependence of the latch-up triggering power $P$ on the ambient temperature $T$. The delay time characteristic is verified to be influenced by the temperature distribution, which is directly affected by the heat dissipation condition. In addition, it is found that the power threshold increases with the decrease in pulse width but that the degree of change with a certain pulse width is constant at different ambient temperatures. Also, the energy absorbed to cause latch-up at a certain temperature is basically sustained at a constant value. As the authors acknowledge, the influencing factors and laws summarized in the investigation may provide guides and references to further experiments and research about latch-up in the CMOS inverter caused by HPM coupling into the digital integrated circuits by the back-door method.